sparc32,sun4m: percpu and global register definitions moved to irq.h
entry.S access percpu + global data defined in sun4m_irq.c - so move the types to irq.h. This makes sparse happy and allow us to utilize asm-offsets later. Also updated a few comments in the sun4m_irq.c file. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2,6 +2,27 @@
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#include <asm/btfixup.h>
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/* sun4m specific type definitions */
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/* This maps direct to CPU specific interrupt registers */
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struct sun4m_irq_percpu {
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u32 pending;
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u32 clear;
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u32 set;
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};
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/* This maps direct to global interrupt registers */
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struct sun4m_irq_global {
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u32 pending;
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u32 mask;
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u32 mask_clear;
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u32 mask_set;
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u32 interrupt_target;
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};
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extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
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extern struct sun4m_irq_global __iomem *sun4m_irq_global;
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/*
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* Platform specific irq configuration
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* The individual platforms assign their platform
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@ -96,20 +96,6 @@
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*/
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struct sun4m_irq_percpu {
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u32 pending;
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u32 clear;
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u32 set;
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};
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struct sun4m_irq_global {
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u32 pending;
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u32 mask;
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u32 mask_clear;
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u32 mask_set;
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u32 interrupt_target;
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};
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/* Code in entry.S needs to get at these register mappings. */
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struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
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struct sun4m_irq_global __iomem *sun4m_irq_global;
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@ -155,8 +141,11 @@ struct sun4m_irq_global __iomem *sun4m_irq_global;
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#define OBP_INT_LEVEL_SBUS 0x30
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#define OBP_INT_LEVEL_VME 0x40
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#define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
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#define SUM4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14)
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static unsigned long irq_mask[0x50] = {
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/* SMP */
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/* 0x00 - SMP */
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0, SUN4M_SOFT_INT(1),
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SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
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SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
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@ -165,7 +154,7 @@ static unsigned long irq_mask[0x50] = {
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SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
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SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
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SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
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/* soft */
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/* 0x10 - soft */
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0, SUN4M_SOFT_INT(1),
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SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
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SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
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@ -174,19 +163,19 @@ static unsigned long irq_mask[0x50] = {
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SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
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SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
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SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
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/* onboard */
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/* 0x20 - onboard */
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0, 0, 0, 0,
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SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
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SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
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SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
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(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
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SUN4M_INT_AUDIO, 0, SUN4M_INT_MODULE_ERR,
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/* sbus */
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/* 0x30 - sbus */
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0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
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0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
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0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
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0, SUN4M_INT_SBUS(6), 0, 0,
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/* vme */
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/* 0x40 - vme */
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0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
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0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
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0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
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@ -319,7 +308,6 @@ struct sun4m_timer_global {
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static struct sun4m_timer_global __iomem *timers_global;
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#define TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
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unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
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@ -396,7 +384,7 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
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master_l10_counter = &timers_global->l10_count;
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err = request_irq(TIMER_IRQ, counter_fn,
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err = request_irq(SUN4M_TIMER_IRQ, counter_fn,
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(IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
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if (err) {
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printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
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