clk: mxs: Fix invalid 32-bit access to frac registers
According to i.MX23 and i.MX28 reference manual [1],[2] the fractional clock control register is 32-bit wide, but is separated in 4 parts. So write instructions must not apply to more than 1 part at once. The clk init for the i.MX28 violates this restriction and all the other accesses on that register suggest that there isn't such a restriction. This patch restricts the access to this register to byte instructions and extends the comment in the init functions. Btw the imx23 init now uses a R-M-W sequence just like imx28 init to avoid any clock glitches. The changes has been tested with a i.MX23 and a i.MX28 board. [1] - http://cache.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf [2] - http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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6793a30a06
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039e597075
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@ -46,11 +46,13 @@ static void __iomem *digctrl;
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#define BP_CLKSEQ_BYPASS_SAIF 0
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#define BP_CLKSEQ_BYPASS_SAIF 0
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#define BP_CLKSEQ_BYPASS_SSP 5
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#define BP_CLKSEQ_BYPASS_SSP 5
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#define BP_SAIF_DIV_FRAC_EN 16
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#define BP_SAIF_DIV_FRAC_EN 16
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#define BP_FRAC_IOFRAC 24
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#define FRAC_IO 3
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static void __init clk_misc_init(void)
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static void __init clk_misc_init(void)
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{
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{
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u32 val;
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u32 val;
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u8 frac;
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/* Gate off cpu clock in WFI for power saving */
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/* Gate off cpu clock in WFI for power saving */
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writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
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writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
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@ -72,9 +74,12 @@ static void __init clk_misc_init(void)
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/*
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/*
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* 480 MHz seems too high to be ssp clock source directly,
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* 480 MHz seems too high to be ssp clock source directly,
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* so set frac to get a 288 MHz ref_io.
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* so set frac to get a 288 MHz ref_io.
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* According to reference manual we must access frac bytewise.
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*/
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*/
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writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
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frac = readb_relaxed(FRAC + FRAC_IO);
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writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
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frac &= ~0x3f;
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frac |= 30;
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writeb_relaxed(frac, FRAC + FRAC_IO);
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}
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}
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static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
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static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
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@ -53,8 +53,9 @@ static void __iomem *clkctrl;
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#define BP_ENET_SLEEP 31
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#define BP_ENET_SLEEP 31
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#define BP_CLKSEQ_BYPASS_SAIF0 0
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#define BP_CLKSEQ_BYPASS_SAIF0 0
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#define BP_CLKSEQ_BYPASS_SSP0 3
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#define BP_CLKSEQ_BYPASS_SSP0 3
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#define BP_FRAC0_IO1FRAC 16
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#define BP_FRAC0_IO0FRAC 24
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#define FRAC0_IO1 2
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#define FRAC0_IO0 3
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static void __iomem *digctrl;
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static void __iomem *digctrl;
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#define DIGCTRL digctrl
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#define DIGCTRL digctrl
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@ -85,6 +86,7 @@ int mxs_saif_clkmux_select(unsigned int clkmux)
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static void __init clk_misc_init(void)
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static void __init clk_misc_init(void)
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{
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{
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u32 val;
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u32 val;
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u8 frac;
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/* Gate off cpu clock in WFI for power saving */
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/* Gate off cpu clock in WFI for power saving */
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writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
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writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
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@ -118,11 +120,16 @@ static void __init clk_misc_init(void)
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/*
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/*
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* 480 MHz seems too high to be ssp clock source directly,
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* 480 MHz seems too high to be ssp clock source directly,
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* so set frac0 to get a 288 MHz ref_io0 and ref_io1.
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* so set frac0 to get a 288 MHz ref_io0 and ref_io1.
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* According to reference manual we must access frac0 bytewise.
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*/
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*/
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val = readl_relaxed(FRAC0);
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frac = readb_relaxed(FRAC0 + FRAC0_IO0);
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val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
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frac &= ~0x3f;
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val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
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frac |= 30;
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writel_relaxed(val, FRAC0);
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writeb_relaxed(frac, FRAC0 + FRAC0_IO0);
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frac = readb_relaxed(FRAC0 + FRAC0_IO1);
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frac &= ~0x3f;
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frac |= 30;
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writeb_relaxed(frac, FRAC0 + FRAC0_IO1);
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}
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}
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static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
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static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
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@ -16,6 +16,8 @@
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include "clk.h"
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#include "clk.h"
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#define BF_CLKGATE BIT(7)
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/**
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/**
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* struct clk_ref - mxs reference clock
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* struct clk_ref - mxs reference clock
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* @hw: clk_hw for the reference clock
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* @hw: clk_hw for the reference clock
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@ -39,7 +41,7 @@ static int clk_ref_enable(struct clk_hw *hw)
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{
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{
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struct clk_ref *ref = to_clk_ref(hw);
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struct clk_ref *ref = to_clk_ref(hw);
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writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
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writeb_relaxed(BF_CLKGATE, ref->reg + ref->idx + CLR);
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return 0;
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return 0;
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}
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}
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@ -48,7 +50,7 @@ static void clk_ref_disable(struct clk_hw *hw)
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{
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{
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struct clk_ref *ref = to_clk_ref(hw);
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struct clk_ref *ref = to_clk_ref(hw);
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writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
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writeb_relaxed(BF_CLKGATE, ref->reg + ref->idx + SET);
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}
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}
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static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
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static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
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@ -56,7 +58,7 @@ static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
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{
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{
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struct clk_ref *ref = to_clk_ref(hw);
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struct clk_ref *ref = to_clk_ref(hw);
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u64 tmp = parent_rate;
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u64 tmp = parent_rate;
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u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f;
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u8 frac = readb_relaxed(ref->reg + ref->idx) & 0x3f;
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tmp *= 18;
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tmp *= 18;
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do_div(tmp, frac);
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do_div(tmp, frac);
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@ -93,8 +95,7 @@ static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
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struct clk_ref *ref = to_clk_ref(hw);
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struct clk_ref *ref = to_clk_ref(hw);
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unsigned long flags;
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unsigned long flags;
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u64 tmp = parent_rate;
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u64 tmp = parent_rate;
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u32 val;
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u8 frac, val;
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u8 frac, shift = ref->idx * 8;
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tmp = tmp * 18 + rate / 2;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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do_div(tmp, rate);
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@ -107,10 +108,10 @@ static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
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spin_lock_irqsave(&mxs_lock, flags);
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spin_lock_irqsave(&mxs_lock, flags);
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val = readl_relaxed(ref->reg);
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val = readb_relaxed(ref->reg + ref->idx);
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val &= ~(0x3f << shift);
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val &= ~0x3f;
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val |= frac << shift;
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val |= frac;
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writel_relaxed(val, ref->reg);
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writeb_relaxed(val, ref->reg + ref->idx);
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spin_unlock_irqrestore(&mxs_lock, flags);
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spin_unlock_irqrestore(&mxs_lock, flags);
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