Merge tag 'drm-intel-fixes-2018-05-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
- Increase LVDS panel timeout to 5s to avoid spurious *ERROR* - Fix 2 WARNS: BIOS framebuffer related (FDO #105992) and eDP cdclk mismatch * tag 'drm-intel-fixes-2018-05-09' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915: Fix drm:intel_enable_lvds ERROR message in kernel log drm/i915: Correctly populate user mode h/vdisplay with pipe src size during readout drm/i915: Adjust eDP's logical vco in a reliable place.
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commit
03a0a3e572
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@ -2302,9 +2302,44 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
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return 0;
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}
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static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
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struct intel_crtc *crtc;
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struct intel_crtc_state *crtc_state;
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int vco, i;
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vco = intel_state->cdclk.logical.vco;
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if (!vco)
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vco = dev_priv->skl_preferred_vco_freq;
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for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
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if (!crtc_state->base.enable)
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continue;
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if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
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continue;
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/*
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* DPLL0 VCO may need to be adjusted to get the correct
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* clock for eDP. This will affect cdclk as well.
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*/
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switch (crtc_state->port_clock / 2) {
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case 108000:
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case 216000:
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vco = 8640000;
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break;
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default:
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vco = 8100000;
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break;
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}
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}
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return vco;
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}
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static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->dev);
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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int min_cdclk, cdclk, vco;
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@ -2312,9 +2347,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
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if (min_cdclk < 0)
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return min_cdclk;
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vco = intel_state->cdclk.logical.vco;
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if (!vco)
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vco = dev_priv->skl_preferred_vco_freq;
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vco = skl_dpll0_vco(intel_state);
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/*
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* FIXME should also account for plane ratio
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@ -15178,6 +15178,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
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memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
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if (crtc_state->base.active) {
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intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
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crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
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crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
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intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
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WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
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@ -1881,26 +1881,6 @@ found:
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reduce_m_n);
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}
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/*
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* DPLL0 VCO may need to be adjusted to get the correct
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* clock for eDP. This will affect cdclk as well.
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*/
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if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
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int vco;
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switch (pipe_config->port_clock / 2) {
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case 108000:
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case 216000:
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vco = 8640000;
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break;
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default:
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vco = 8100000;
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break;
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}
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to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
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}
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if (!HAS_DDI(dev_priv))
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intel_dp_set_clock(encoder, pipe_config);
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@ -326,7 +326,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder,
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I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
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POSTING_READ(lvds_encoder->reg);
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if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
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if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
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DRM_ERROR("timed out waiting for panel to power on\n");
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intel_panel_enable_backlight(pipe_config, conn_state);
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