KVM fixes for v4.16-rc4
x86:
- fix NULL dereference when using userspace lapic
- optimize spectre v1 mitigations by allowing guests to use LFENCE
- make microcode revision configurable to prevent guests from
unnecessarily blacklisting spectre v2 mitigation features
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Radim Krčmář:
"x86:
- fix NULL dereference when using userspace lapic
- optimize spectre v1 mitigations by allowing guests to use LFENCE
- make microcode revision configurable to prevent guests from
unnecessarily blacklisting spectre v2 mitigation feature"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: x86: fix vcpu initialization with userspace lapic
KVM: X86: Allow userspace to define the microcode version
KVM: X86: Introduce kvm_get_msr_feature()
KVM: SVM: Add MSR-based feature support for serializing LFENCE
KVM: x86: Add a framework for supporting MSR-based features
hifive-unleashed-5.1
Linus Torvalds
commit
03a6c2592f
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@ -123,14 +123,15 @@ memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the
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flag KVM_VM_MIPS_VZ.
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4.3 KVM_GET_MSR_INDEX_LIST
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4.3 KVM_GET_MSR_INDEX_LIST, KVM_GET_MSR_FEATURE_INDEX_LIST
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Capability: basic
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Capability: basic, KVM_CAP_GET_MSR_FEATURES for KVM_GET_MSR_FEATURE_INDEX_LIST
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Architectures: x86
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Type: system
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Type: system ioctl
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Parameters: struct kvm_msr_list (in/out)
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Returns: 0 on success; -1 on error
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Errors:
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EFAULT: the msr index list cannot be read from or written to
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E2BIG: the msr index list is to be to fit in the array specified by
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the user.
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@ -139,16 +140,23 @@ struct kvm_msr_list {
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__u32 indices[0];
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};
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This ioctl returns the guest msrs that are supported. The list varies
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by kvm version and host processor, but does not change otherwise. The
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user fills in the size of the indices array in nmsrs, and in return
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kvm adjusts nmsrs to reflect the actual number of msrs and fills in
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the indices array with their numbers.
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The user fills in the size of the indices array in nmsrs, and in return
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kvm adjusts nmsrs to reflect the actual number of msrs and fills in the
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indices array with their numbers.
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KVM_GET_MSR_INDEX_LIST returns the guest msrs that are supported. The list
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varies by kvm version and host processor, but does not change otherwise.
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Note: if kvm indicates supports MCE (KVM_CAP_MCE), then the MCE bank MSRs are
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not returned in the MSR list, as different vcpus can have a different number
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of banks, as set via the KVM_X86_SETUP_MCE ioctl.
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KVM_GET_MSR_FEATURE_INDEX_LIST returns the list of MSRs that can be passed
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to the KVM_GET_MSRS system ioctl. This lets userspace probe host capabilities
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and processor features that are exposed via MSRs (e.g., VMX capabilities).
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This list also varies by kvm version and host processor, but does not change
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otherwise.
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4.4 KVM_CHECK_EXTENSION
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@ -475,14 +483,22 @@ Support for this has been removed. Use KVM_SET_GUEST_DEBUG instead.
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4.18 KVM_GET_MSRS
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Capability: basic
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Capability: basic (vcpu), KVM_CAP_GET_MSR_FEATURES (system)
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Architectures: x86
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Type: vcpu ioctl
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Type: system ioctl, vcpu ioctl
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Parameters: struct kvm_msrs (in/out)
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Returns: 0 on success, -1 on error
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Returns: number of msrs successfully returned;
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-1 on error
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When used as a system ioctl:
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Reads the values of MSR-based features that are available for the VM. This
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is similar to KVM_GET_SUPPORTED_CPUID, but it returns MSR indices and values.
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The list of msr-based features can be obtained using KVM_GET_MSR_FEATURE_INDEX_LIST
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in a system ioctl.
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When used as a vcpu ioctl:
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Reads model-specific registers from the vcpu. Supported msr indices can
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be obtained using KVM_GET_MSR_INDEX_LIST.
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be obtained using KVM_GET_MSR_INDEX_LIST in a system ioctl.
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struct kvm_msrs {
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__u32 nmsrs; /* number of msrs in entries */
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@ -507,6 +507,7 @@ struct kvm_vcpu_arch {
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u64 smi_count;
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bool tpr_access_reporting;
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u64 ia32_xss;
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u64 microcode_version;
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/*
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* Paging state of the vcpu
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@ -1095,6 +1096,8 @@ struct kvm_x86_ops {
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int (*mem_enc_op)(struct kvm *kvm, void __user *argp);
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int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
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int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
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int (*get_msr_feature)(struct kvm_msr_entry *entry);
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};
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struct kvm_arch_async_pf {
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@ -2002,14 +2002,13 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
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void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
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{
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struct kvm_lapic *apic;
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struct kvm_lapic *apic = vcpu->arch.apic;
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int i;
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apic_debug("%s\n", __func__);
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if (!apic)
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return;
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ASSERT(vcpu);
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apic = vcpu->arch.apic;
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ASSERT(apic != NULL);
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apic_debug("%s\n", __func__);
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/* Stop the timer in case it's a reset to an active apic */
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hrtimer_cancel(&apic->lapic_timer.timer);
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@ -2568,7 +2567,6 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
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pe = xchg(&apic->pending_events, 0);
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if (test_bit(KVM_APIC_INIT, &pe)) {
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kvm_lapic_reset(vcpu, true);
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kvm_vcpu_reset(vcpu, true);
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if (kvm_vcpu_is_bsp(apic->vcpu))
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vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
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@ -179,6 +179,8 @@ struct vcpu_svm {
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uint64_t sysenter_eip;
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uint64_t tsc_aux;
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u64 msr_decfg;
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u64 next_rip;
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u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
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@ -1906,6 +1908,7 @@ static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
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u32 dummy;
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u32 eax = 1;
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vcpu->arch.microcode_version = 0x01000065;
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svm->spec_ctrl = 0;
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if (!init_event) {
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@ -3870,6 +3873,22 @@ static int cr8_write_interception(struct vcpu_svm *svm)
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return 0;
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}
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static int svm_get_msr_feature(struct kvm_msr_entry *msr)
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{
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msr->data = 0;
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switch (msr->index) {
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case MSR_F10H_DECFG:
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if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
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msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
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break;
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default:
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return 1;
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}
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return 0;
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}
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static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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@ -3945,9 +3964,6 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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msr_info->data = svm->spec_ctrl;
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break;
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case MSR_IA32_UCODE_REV:
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msr_info->data = 0x01000065;
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break;
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case MSR_F15H_IC_CFG: {
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int family, model;
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@ -3965,6 +3981,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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msr_info->data = 0x1E;
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}
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break;
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case MSR_F10H_DECFG:
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msr_info->data = svm->msr_decfg;
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break;
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default:
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return kvm_get_msr_common(vcpu, msr_info);
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}
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@ -4143,6 +4162,24 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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case MSR_VM_IGNNE:
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vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
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break;
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case MSR_F10H_DECFG: {
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struct kvm_msr_entry msr_entry;
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msr_entry.index = msr->index;
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if (svm_get_msr_feature(&msr_entry))
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return 1;
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/* Check the supported bits */
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if (data & ~msr_entry.data)
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return 1;
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/* Don't allow the guest to change a bit, #GP */
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if (!msr->host_initiated && (data ^ msr_entry.data))
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return 1;
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svm->msr_decfg = data;
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break;
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}
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case MSR_IA32_APICBASE:
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if (kvm_vcpu_apicv_active(vcpu))
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avic_update_vapic_bar(to_svm(vcpu), data);
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@ -6833,6 +6870,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
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.vcpu_unblocking = svm_vcpu_unblocking,
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.update_bp_intercept = update_bp_intercept,
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.get_msr_feature = svm_get_msr_feature,
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.get_msr = svm_get_msr,
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.set_msr = svm_set_msr,
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.get_segment_base = svm_get_segment_base,
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@ -3227,6 +3227,11 @@ static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
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return !(val & ~valid_bits);
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}
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static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
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{
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return 1;
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}
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/*
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* Reads an msr value (of 'msr_index') into 'pdata'.
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* Returns 0 on success, non-0 otherwise.
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@ -5767,6 +5772,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
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vmx->rmode.vm86_active = 0;
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vmx->spec_ctrl = 0;
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vcpu->arch.microcode_version = 0x100000000ULL;
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vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
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kvm_set_cr8(vcpu, 0);
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@ -12297,6 +12303,7 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
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.vcpu_put = vmx_vcpu_put,
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.update_bp_intercept = update_exception_bitmap,
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.get_msr_feature = vmx_get_msr_feature,
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.get_msr = vmx_get_msr,
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.set_msr = vmx_set_msr,
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.get_segment_base = vmx_get_segment_base,
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@ -1049,6 +1049,45 @@ static u32 emulated_msrs[] = {
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static unsigned num_emulated_msrs;
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/*
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* List of msr numbers which are used to expose MSR-based features that
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* can be used by a hypervisor to validate requested CPU features.
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*/
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static u32 msr_based_features[] = {
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MSR_F10H_DECFG,
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MSR_IA32_UCODE_REV,
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};
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static unsigned int num_msr_based_features;
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static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
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{
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switch (msr->index) {
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case MSR_IA32_UCODE_REV:
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rdmsrl(msr->index, msr->data);
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break;
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default:
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if (kvm_x86_ops->get_msr_feature(msr))
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return 1;
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||||
}
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return 0;
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}
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static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
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{
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struct kvm_msr_entry msr;
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int r;
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msr.index = index;
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r = kvm_get_msr_feature(&msr);
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if (r)
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return r;
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*data = msr.data;
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return 0;
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}
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||||
|
||||
bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
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||||
{
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||||
if (efer & efer_reserved_bits)
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||||
|
|
@ -2222,7 +2261,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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|||
|
||||
switch (msr) {
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case MSR_AMD64_NB_CFG:
|
||||
case MSR_IA32_UCODE_REV:
|
||||
case MSR_IA32_UCODE_WRITE:
|
||||
case MSR_VM_HSAVE_PA:
|
||||
case MSR_AMD64_PATCH_LOADER:
|
||||
|
|
@ -2230,6 +2268,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|||
case MSR_AMD64_DC_CFG:
|
||||
break;
|
||||
|
||||
case MSR_IA32_UCODE_REV:
|
||||
if (msr_info->host_initiated)
|
||||
vcpu->arch.microcode_version = data;
|
||||
break;
|
||||
case MSR_EFER:
|
||||
return set_efer(vcpu, data);
|
||||
case MSR_K7_HWCR:
|
||||
|
|
@ -2525,7 +2567,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|||
msr_info->data = 0;
|
||||
break;
|
||||
case MSR_IA32_UCODE_REV:
|
||||
msr_info->data = 0x100000000ULL;
|
||||
msr_info->data = vcpu->arch.microcode_version;
|
||||
break;
|
||||
case MSR_MTRRcap:
|
||||
case 0x200 ... 0x2ff:
|
||||
|
|
@ -2680,13 +2722,11 @@ static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
|
|||
int (*do_msr)(struct kvm_vcpu *vcpu,
|
||||
unsigned index, u64 *data))
|
||||
{
|
||||
int i, idx;
|
||||
int i;
|
||||
|
||||
idx = srcu_read_lock(&vcpu->kvm->srcu);
|
||||
for (i = 0; i < msrs->nmsrs; ++i)
|
||||
if (do_msr(vcpu, entries[i].index, &entries[i].data))
|
||||
break;
|
||||
srcu_read_unlock(&vcpu->kvm->srcu, idx);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
|
@ -2785,6 +2825,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
|
|||
case KVM_CAP_SET_BOOT_CPU_ID:
|
||||
case KVM_CAP_SPLIT_IRQCHIP:
|
||||
case KVM_CAP_IMMEDIATE_EXIT:
|
||||
case KVM_CAP_GET_MSR_FEATURES:
|
||||
r = 1;
|
||||
break;
|
||||
case KVM_CAP_ADJUST_CLOCK:
|
||||
|
|
@ -2899,6 +2940,31 @@ long kvm_arch_dev_ioctl(struct file *filp,
|
|||
goto out;
|
||||
r = 0;
|
||||
break;
|
||||
case KVM_GET_MSR_FEATURE_INDEX_LIST: {
|
||||
struct kvm_msr_list __user *user_msr_list = argp;
|
||||
struct kvm_msr_list msr_list;
|
||||
unsigned int n;
|
||||
|
||||
r = -EFAULT;
|
||||
if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
|
||||
goto out;
|
||||
n = msr_list.nmsrs;
|
||||
msr_list.nmsrs = num_msr_based_features;
|
||||
if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
|
||||
goto out;
|
||||
r = -E2BIG;
|
||||
if (n < msr_list.nmsrs)
|
||||
goto out;
|
||||
r = -EFAULT;
|
||||
if (copy_to_user(user_msr_list->indices, &msr_based_features,
|
||||
num_msr_based_features * sizeof(u32)))
|
||||
goto out;
|
||||
r = 0;
|
||||
break;
|
||||
}
|
||||
case KVM_GET_MSRS:
|
||||
r = msr_io(NULL, argp, do_get_msr_feature, 1);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
r = -EINVAL;
|
||||
|
|
@ -3636,12 +3702,18 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
|
|||
r = 0;
|
||||
break;
|
||||
}
|
||||
case KVM_GET_MSRS:
|
||||
case KVM_GET_MSRS: {
|
||||
int idx = srcu_read_lock(&vcpu->kvm->srcu);
|
||||
r = msr_io(vcpu, argp, do_get_msr, 1);
|
||||
srcu_read_unlock(&vcpu->kvm->srcu, idx);
|
||||
break;
|
||||
case KVM_SET_MSRS:
|
||||
}
|
||||
case KVM_SET_MSRS: {
|
||||
int idx = srcu_read_lock(&vcpu->kvm->srcu);
|
||||
r = msr_io(vcpu, argp, do_set_msr, 0);
|
||||
srcu_read_unlock(&vcpu->kvm->srcu, idx);
|
||||
break;
|
||||
}
|
||||
case KVM_TPR_ACCESS_REPORTING: {
|
||||
struct kvm_tpr_access_ctl tac;
|
||||
|
||||
|
|
@ -4464,6 +4536,19 @@ static void kvm_init_msr_list(void)
|
|||
j++;
|
||||
}
|
||||
num_emulated_msrs = j;
|
||||
|
||||
for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
|
||||
struct kvm_msr_entry msr;
|
||||
|
||||
msr.index = msr_based_features[i];
|
||||
if (kvm_get_msr_feature(&msr))
|
||||
continue;
|
||||
|
||||
if (j < i)
|
||||
msr_based_features[j] = msr_based_features[i];
|
||||
j++;
|
||||
}
|
||||
num_msr_based_features = j;
|
||||
}
|
||||
|
||||
static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
|
||||
|
|
@ -7975,7 +8060,6 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
|
|||
kvm_vcpu_mtrr_init(vcpu);
|
||||
vcpu_load(vcpu);
|
||||
kvm_vcpu_reset(vcpu, false);
|
||||
kvm_lapic_reset(vcpu, false);
|
||||
kvm_mmu_setup(vcpu);
|
||||
vcpu_put(vcpu);
|
||||
return 0;
|
||||
|
|
@ -8018,6 +8102,8 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
|
|||
|
||||
void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
|
||||
{
|
||||
kvm_lapic_reset(vcpu, init_event);
|
||||
|
||||
vcpu->arch.hflags = 0;
|
||||
|
||||
vcpu->arch.smi_pending = 0;
|
||||
|
|
|
|||
|
|
@ -761,6 +761,7 @@ struct kvm_ppc_resize_hpt {
|
|||
#define KVM_TRACE_PAUSE __KVM_DEPRECATED_MAIN_0x07
|
||||
#define KVM_TRACE_DISABLE __KVM_DEPRECATED_MAIN_0x08
|
||||
#define KVM_GET_EMULATED_CPUID _IOWR(KVMIO, 0x09, struct kvm_cpuid2)
|
||||
#define KVM_GET_MSR_FEATURE_INDEX_LIST _IOWR(KVMIO, 0x0a, struct kvm_msr_list)
|
||||
|
||||
/*
|
||||
* Extension capability list.
|
||||
|
|
@ -934,6 +935,7 @@ struct kvm_ppc_resize_hpt {
|
|||
#define KVM_CAP_S390_AIS_MIGRATION 150
|
||||
#define KVM_CAP_PPC_GET_CPU_CHAR 151
|
||||
#define KVM_CAP_S390_BPB 152
|
||||
#define KVM_CAP_GET_MSR_FEATURES 153
|
||||
|
||||
#ifdef KVM_CAP_IRQ_ROUTING
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue