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KVM: PPC: Book3S PR: Handle PP0 page-protection bit in guest HPTEs

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64-bit POWER processors have a three-bit field for page protection in
the hashed page table entry (HPTE).  Currently we only interpret the two
bits that were present in older versions of the architecture.  The only
defined combination that has the new bit set is 110, meaning read-only
for supervisor and no access for user mode.

This adds code to kvmppc_mmu_book3s_64_xlate() to interpret the extra
bit appropriately.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Paul Mackerras 2013-09-20 14:52:46 +10:00 committed by Alexander Graf
parent c9029c341d
commit 03a9c90334
1 changed files with 3 additions and 0 deletions
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3
arch/powerpc/kvm/book3s_64_mmu.c
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@ -298,6 +298,8 @@ do_second:
v = pteg[i];
r = pteg[i+1];
pp = (r & HPTE_R_PP) | key;
if (r & HPTE_R_PP0)
pp |= 8;
gpte->eaddr = eaddr;
gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, eaddr, data);
@ -319,6 +321,7 @@ do_second:
case 3:
case 5:
case 7:
case 10:
gpte->may_read = true;
break;
}