dmaengine/amba-pl08x: Add prep_single_byte_llis() routine
Code for creating single byte llis is present at several places. Create a routine to avoid code redundancy. Also, we don't need one lli per single byte transfer, we can have single lli to do all single byte transfer. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -559,6 +559,14 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
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bd->remainder -= len;
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}
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static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
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u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
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{
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*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
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pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
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(*total_bytes) += len;
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}
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/*
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* This fills in the table of LLIs for the transfer descriptor
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* Note that we assume we never have to change the burst sizes
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@ -570,7 +578,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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struct pl08x_bus_data *mbus, *sbus;
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struct pl08x_lli_build_data bd;
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int num_llis = 0;
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u32 cctl;
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u32 cctl, early_bytes = 0;
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size_t max_bytes_per_lli, total_bytes = 0;
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struct pl08x_lli *llis_va;
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@ -619,29 +627,27 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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mbus == &bd.srcbus ? "src" : "dst",
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sbus == &bd.srcbus ? "src" : "dst");
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if (txd->len < mbus->buswidth) {
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/* Less than a bus width available - send as single bytes */
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while (bd.remainder) {
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dev_vdbg(&pl08x->adev->dev,
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"%s single byte LLIs for a transfer of "
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"less than a bus width (remain 0x%08x)\n",
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__func__, bd.remainder);
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cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
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pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
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total_bytes++;
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}
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} else {
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/* Make one byte LLIs until master bus is aligned */
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while ((mbus->addr) % (mbus->buswidth)) {
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dev_vdbg(&pl08x->adev->dev,
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"%s adjustment lli for less than bus width "
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"(remain 0x%08x)\n",
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__func__, bd.remainder);
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cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
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pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
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total_bytes++;
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}
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/*
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* Send byte by byte for following cases
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* - Less than a bus width available
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* - until master bus is aligned
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*/
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if (bd.remainder < mbus->buswidth)
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early_bytes = bd.remainder;
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else if ((mbus->addr) % (mbus->buswidth)) {
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early_bytes = mbus->buswidth - (mbus->addr) % (mbus->buswidth);
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if ((bd.remainder - early_bytes) < mbus->buswidth)
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early_bytes = bd.remainder;
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}
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if (early_bytes) {
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dev_vdbg(&pl08x->adev->dev, "%s byte width LLIs "
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"(remain 0x%08x)\n", __func__, bd.remainder);
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prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
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&total_bytes);
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}
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if (bd.remainder) {
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/*
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* Master now aligned
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* - if slave is not then we must set its width down
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@ -692,13 +698,12 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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/*
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* Send any odd bytes
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*/
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while (bd.remainder) {
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cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
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if (bd.remainder) {
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dev_vdbg(&pl08x->adev->dev,
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"%s align with boundary, single odd byte (remain %zu)\n",
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"%s align with boundary, send odd bytes (remain %zu)\n",
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__func__, bd.remainder);
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pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
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total_bytes++;
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prep_byte_width_lli(&bd, &cctl, bd.remainder,
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num_llis++, &total_bytes);
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}
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}
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