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clk: mediatek: Add MUX_FLAGS macro 

This is required to mark outputs of certain MUXes as CLK_IS_CRITICAL.

Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Acked-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
hifive-unleashed-5.1
Jasper Mattsson 2019-02-14 17:32:18 +01:00 committed by Stephen Boyd
parent bfeffd1552
commit 03c4fda603
1 changed files with 6 additions and 2 deletions
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8
drivers/clk/mediatek/clk-mtk.h
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@ -111,7 +111,11 @@ struct mtk_composite {
MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
_gate, CLK_SET_RATE_PARENT)
#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
#define MUX(_id, _name, _parents, _reg, _shift, _width) \
MUX_FLAGS(_id, _name, _parents, _reg, \
_shift, _width, CLK_SET_RATE_PARENT)
#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
.id = _id, \
.name = _name, \
.mux_reg = _reg, \
@ -121,7 +125,7 @@ struct mtk_composite {
.divider_shift = -1, \
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_SET_RATE_PARENT, \
.flags = _flags, \
}
#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \