Merge branch 'qed-roce-iscsi'
Yuval Mintz says: ==================== qed: RocE & iSCSI infrastructure We plan on sending 2 new protocol drivers in the imminent future - both our RoCE [qedr] and iSCSI [qedi] drivers. As both submissions would be rather massive and in order to avoid collisions between them, the common infrastructure on the qed side was prepared as an independent patch-series to be sent ahead of those 2 submissions. This patch series introduces in QED 2 new 'ids' - one for iscsi and one for roce. It then goes and adds logic required for configuring said protocols in HW. Notice it *doesn't* actually add any client using said ids, but rather only the infrastructure to allow their later usage. What this patch doesn't contain is the slowpath protocol-configuration toward the firmware. I.e., it contains register-setting logic, memory allocations, etc., but not actual flow-related configuration specific to the protocl. Those would be sent as part of the protocol driver submissions. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
03c7f70bee
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@ -127,6 +127,8 @@ struct qed_tunn_update_params {
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*/
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enum qed_pci_personality {
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QED_PCI_ETH,
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QED_PCI_ISCSI,
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QED_PCI_ETH_ROCE,
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QED_PCI_DEFAULT /* default in shmem */
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};
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@ -170,6 +172,8 @@ enum QED_PORT_MODE {
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enum qed_dev_cap {
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QED_DEV_CAP_ETH,
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QED_DEV_CAP_ISCSI,
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QED_DEV_CAP_ROCE,
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};
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struct qed_hw_info {
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@ -183,6 +187,8 @@ struct qed_hw_info {
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#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
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#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
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#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
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RESC_NUM(_p_hwfn, resc))
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#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
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u8 num_tc;
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@ -255,6 +261,7 @@ struct qed_qm_info {
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u8 pure_lb_pq;
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u8 offload_pq;
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u8 pure_ack_pq;
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u8 ooo_pq;
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u8 vf_queues_offset;
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u16 num_pqs;
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u16 num_vf_pqs;
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@ -267,6 +274,7 @@ struct qed_qm_info {
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u8 pf_wfq;
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u32 pf_rl;
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struct qed_wfq_data *wfq_data;
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u8 num_pf_rls;
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};
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struct storm_stats {
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@ -312,6 +320,7 @@ struct qed_hwfn {
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bool hw_init_done;
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u8 num_funcs_on_engine;
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u8 enabled_func_idx;
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/* BAR access */
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void __iomem *regview;
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@ -350,6 +359,9 @@ struct qed_hwfn {
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/* Protocol related */
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struct qed_pf_params pf_params;
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bool b_rdma_enabled_in_prs;
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u32 rdma_prs_search_reg;
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/* Array of sb_info of all status blocks */
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struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
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u16 num_sbs;
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@ -555,6 +567,7 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
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}
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#define PURE_LB_TC 8
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#define OOO_LB_TC 9
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int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
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void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
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File diff suppressed because it is too large
Load diff
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@ -21,6 +21,14 @@ struct qed_cxt_info {
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enum protocol_type type;
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};
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#define MAX_TID_BLOCKS 512
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struct qed_tid_mem {
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u32 tid_size;
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u32 num_tids_per_block;
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u32 waste;
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u8 *blocks[MAX_TID_BLOCKS]; /* 4K */
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};
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/**
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* @brief qed_cxt_acquire - Acquire a new cid of a specific protocol type
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*
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@ -46,8 +54,22 @@ int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
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int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn,
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struct qed_cxt_info *p_info);
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/**
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* @brief qed_cxt_get_tid_mem_info
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*
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* @param p_hwfn
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* @param p_info
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*
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* @return int
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*/
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int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
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struct qed_tid_mem *p_info);
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#define QED_CXT_ISCSI_TID_SEG PROTOCOLID_ISCSI
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#define QED_CXT_ROCE_TID_SEG PROTOCOLID_ROCE
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enum qed_cxt_elem_type {
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QED_ELEM_CXT,
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QED_ELEM_SRQ,
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QED_ELEM_TASK
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};
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@ -149,4 +171,6 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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void qed_cxt_release_cid(struct qed_hwfn *p_hwfn,
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u32 cid);
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#define QED_CTX_WORKING_MEM 0
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#define QED_CTX_FL_MEM 1
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#endif
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@ -17,6 +17,7 @@
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/vmalloc.h>
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#include <linux/etherdevice.h>
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#include <linux/qed/qed_chain.h>
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#include <linux/qed/qed_if.h>
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@ -160,9 +161,13 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
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struct qed_qm_info *qm_info = &p_hwfn->qm_info;
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struct init_qm_port_params *p_qm_port;
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bool init_rdma_offload_pq = false;
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bool init_pure_ack_pq = false;
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bool init_ooo_pq = false;
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u16 num_pqs, multi_cos_tcs = 1;
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u8 pf_wfq = qm_info->pf_wfq;
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u32 pf_rl = qm_info->pf_rl;
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u16 num_pf_rls = 0;
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u16 num_vfs = 0;
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#ifdef CONFIG_QED_SRIOV
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@ -174,6 +179,25 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
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num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
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if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
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num_pqs++; /* for RoCE queue */
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init_rdma_offload_pq = true;
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/* we subtract num_vfs because each require a rate limiter,
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* and one default rate limiter
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*/
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if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
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num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
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num_pqs += num_pf_rls;
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qm_info->num_pf_rls = (u8) num_pf_rls;
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}
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if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
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num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
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init_pure_ack_pq = true;
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init_ooo_pq = true;
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}
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/* Sanity checking that setup requires legal number of resources */
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if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
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DP_ERR(p_hwfn,
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@ -211,12 +235,22 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
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/* First init rate limited queues */
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for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
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qm_info->qm_pq_params[curr_queue].tc_id =
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p_hwfn->hw_info.non_offload_tc;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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qm_info->qm_pq_params[curr_queue].rl_valid = 1;
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}
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/* First init per-TC PQs */
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for (i = 0; i < multi_cos_tcs; i++) {
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struct init_qm_pq_params *params =
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&qm_info->qm_pq_params[curr_queue++];
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if (p_hwfn->hw_info.personality == QED_PCI_ETH) {
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if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
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p_hwfn->hw_info.personality == QED_PCI_ETH) {
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params->vport_id = vport_id;
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params->tc_id = p_hwfn->hw_info.non_offload_tc;
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params->wrr_group = 1;
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@ -236,6 +270,32 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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curr_queue++;
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qm_info->offload_pq = 0;
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if (init_rdma_offload_pq) {
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qm_info->offload_pq = curr_queue;
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
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qm_info->qm_pq_params[curr_queue].tc_id =
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p_hwfn->hw_info.offload_tc;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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curr_queue++;
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}
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if (init_pure_ack_pq) {
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qm_info->pure_ack_pq = curr_queue;
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
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qm_info->qm_pq_params[curr_queue].tc_id =
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p_hwfn->hw_info.offload_tc;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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curr_queue++;
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}
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if (init_ooo_pq) {
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qm_info->ooo_pq = curr_queue;
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
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qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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curr_queue++;
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}
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/* Then init per-VF PQs */
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vf_offset = curr_queue;
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for (i = 0; i < num_vfs; i++) {
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@ -370,21 +430,20 @@ int qed_resc_alloc(struct qed_dev *cdev)
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if (!p_hwfn->p_tx_cids) {
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DP_NOTICE(p_hwfn,
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"Failed to allocate memory for Tx Cids\n");
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rc = -ENOMEM;
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goto alloc_err;
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goto alloc_no_mem;
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}
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p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
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if (!p_hwfn->p_rx_cids) {
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DP_NOTICE(p_hwfn,
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"Failed to allocate memory for Rx Cids\n");
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rc = -ENOMEM;
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goto alloc_err;
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goto alloc_no_mem;
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}
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}
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for_each_hwfn(cdev, i) {
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struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
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u32 n_eqes, num_cons;
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/* First allocate the context manager structure */
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rc = qed_cxt_mngr_alloc(p_hwfn);
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@ -433,18 +492,34 @@ int qed_resc_alloc(struct qed_dev *cdev)
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goto alloc_err;
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/* EQ */
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p_eq = qed_eq_alloc(p_hwfn, 256);
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if (!p_eq) {
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rc = -ENOMEM;
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n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
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if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
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num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
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PROTOCOLID_ROCE,
|
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0) * 2;
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n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
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} else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
|
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num_cons =
|
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qed_cxt_get_proto_cid_count(p_hwfn,
|
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PROTOCOLID_ISCSI, 0);
|
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n_eqes += 2 * num_cons;
|
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}
|
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|
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if (n_eqes > 0xFFFF) {
|
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DP_ERR(p_hwfn,
|
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"Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
|
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n_eqes, 0xFFFF);
|
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goto alloc_err;
|
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}
|
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|
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p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
|
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if (!p_eq)
|
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goto alloc_no_mem;
|
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p_hwfn->p_eq = p_eq;
|
||||
|
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p_consq = qed_consq_alloc(p_hwfn);
|
||||
if (!p_consq) {
|
||||
rc = -ENOMEM;
|
||||
goto alloc_err;
|
||||
}
|
||||
if (!p_consq)
|
||||
goto alloc_no_mem;
|
||||
p_hwfn->p_consq = p_consq;
|
||||
|
||||
/* DMA info initialization */
|
||||
|
@ -473,6 +548,8 @@ int qed_resc_alloc(struct qed_dev *cdev)
|
|||
|
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return 0;
|
||||
|
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alloc_no_mem:
|
||||
rc = -ENOMEM;
|
||||
alloc_err:
|
||||
qed_resc_free(cdev);
|
||||
return rc;
|
||||
|
@ -638,6 +715,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
|
|||
struct qed_qm_info *qm_info = &p_hwfn->qm_info;
|
||||
struct qed_qm_common_rt_init_params params;
|
||||
struct qed_dev *cdev = p_hwfn->cdev;
|
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u16 num_pfs, pf_id;
|
||||
u32 concrete_fid;
|
||||
int rc = 0;
|
||||
u8 vf_id;
|
||||
|
@ -686,9 +764,16 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
|
|||
qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
|
||||
qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
|
||||
|
||||
/* Disable relaxed ordering in the PCI config space */
|
||||
qed_wr(p_hwfn, p_ptt, 0x20b4,
|
||||
qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
|
||||
if (QED_IS_BB(p_hwfn->cdev)) {
|
||||
num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
|
||||
for (pf_id = 0; pf_id < num_pfs; pf_id++) {
|
||||
qed_fid_pretend(p_hwfn, p_ptt, pf_id);
|
||||
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
|
||||
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
|
||||
}
|
||||
/* pretend to original PF */
|
||||
qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
|
||||
}
|
||||
|
||||
for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
|
||||
concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
|
||||
|
@ -778,7 +863,8 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
|
|||
}
|
||||
|
||||
/* Protocl Configuration */
|
||||
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
|
||||
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
|
||||
(p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
|
||||
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
|
||||
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
|
||||
|
||||
|
@ -1255,8 +1341,9 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
|
|||
num_features);
|
||||
}
|
||||
|
||||
static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
|
||||
static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
|
||||
{
|
||||
u8 enabled_func_idx = p_hwfn->enabled_func_idx;
|
||||
u32 *resc_start = p_hwfn->hw_info.resc_start;
|
||||
u8 num_funcs = p_hwfn->num_funcs_on_engine;
|
||||
u32 *resc_num = p_hwfn->hw_info.resc_num;
|
||||
|
@ -1280,14 +1367,22 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
|
|||
resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
|
||||
resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
|
||||
resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
|
||||
resc_num[QED_RL] = 8;
|
||||
resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
|
||||
resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
|
||||
resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
|
||||
num_funcs;
|
||||
resc_num[QED_ILT] = 950;
|
||||
resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
|
||||
|
||||
for (i = 0; i < QED_MAX_RESC; i++)
|
||||
resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
|
||||
resc_start[i] = resc_num[i] * enabled_func_idx;
|
||||
|
||||
/* Sanity for ILT */
|
||||
if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
|
||||
DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
|
||||
RESC_START(p_hwfn, QED_ILT),
|
||||
RESC_END(p_hwfn, QED_ILT) - 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
qed_hw_set_feat(p_hwfn);
|
||||
|
||||
|
@ -1317,6 +1412,8 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
|
|||
p_hwfn->hw_info.resc_start[QED_VLAN],
|
||||
p_hwfn->hw_info.resc_num[QED_ILT],
|
||||
p_hwfn->hw_info.resc_start[QED_ILT]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
|
||||
|
@ -1471,14 +1568,20 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
|
|||
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
|
||||
__set_bit(QED_DEV_CAP_ETH,
|
||||
&p_hwfn->hw_info.device_capabilities);
|
||||
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
|
||||
__set_bit(QED_DEV_CAP_ISCSI,
|
||||
&p_hwfn->hw_info.device_capabilities);
|
||||
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
|
||||
__set_bit(QED_DEV_CAP_ROCE,
|
||||
&p_hwfn->hw_info.device_capabilities);
|
||||
|
||||
return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
|
||||
}
|
||||
|
||||
static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
|
||||
{
|
||||
u32 reg_function_hide, tmp, eng_mask;
|
||||
u8 num_funcs;
|
||||
u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
|
||||
u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
|
||||
|
||||
num_funcs = MAX_NUM_PFS_BB;
|
||||
|
||||
|
@ -1508,9 +1611,19 @@ static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
|
|||
num_funcs++;
|
||||
tmp >>= 0x1;
|
||||
}
|
||||
|
||||
/* Get the PF index within the enabled functions */
|
||||
low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
|
||||
tmp = reg_function_hide & eng_mask & low_pfs_mask;
|
||||
while (tmp) {
|
||||
if (tmp & 0x1)
|
||||
enabled_func_idx--;
|
||||
tmp >>= 0x1;
|
||||
}
|
||||
}
|
||||
|
||||
p_hwfn->num_funcs_on_engine = num_funcs;
|
||||
p_hwfn->enabled_func_idx = enabled_func_idx;
|
||||
|
||||
DP_VERBOSE(p_hwfn,
|
||||
NETIF_MSG_PROBE,
|
||||
|
@ -1580,9 +1693,7 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
|
|||
|
||||
qed_get_num_funcs(p_hwfn, p_ptt);
|
||||
|
||||
qed_hw_get_resc(p_hwfn);
|
||||
|
||||
return rc;
|
||||
return qed_hw_get_resc(p_hwfn);
|
||||
}
|
||||
|
||||
static int qed_get_dev_info(struct qed_dev *cdev)
|
||||
|
@ -1779,92 +1890,285 @@ void qed_hw_remove(struct qed_dev *cdev)
|
|||
qed_iov_free_hw_info(cdev);
|
||||
}
|
||||
|
||||
static void qed_chain_free_next_ptr(struct qed_dev *cdev,
|
||||
struct qed_chain *p_chain)
|
||||
{
|
||||
void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
|
||||
dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
|
||||
struct qed_chain_next *p_next;
|
||||
u32 size, i;
|
||||
|
||||
if (!p_virt)
|
||||
return;
|
||||
|
||||
size = p_chain->elem_size * p_chain->usable_per_page;
|
||||
|
||||
for (i = 0; i < p_chain->page_cnt; i++) {
|
||||
if (!p_virt)
|
||||
break;
|
||||
|
||||
p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
|
||||
p_virt_next = p_next->next_virt;
|
||||
p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
|
||||
|
||||
dma_free_coherent(&cdev->pdev->dev,
|
||||
QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
|
||||
|
||||
p_virt = p_virt_next;
|
||||
p_phys = p_phys_next;
|
||||
}
|
||||
}
|
||||
|
||||
static void qed_chain_free_single(struct qed_dev *cdev,
|
||||
struct qed_chain *p_chain)
|
||||
{
|
||||
if (!p_chain->p_virt_addr)
|
||||
return;
|
||||
|
||||
dma_free_coherent(&cdev->pdev->dev,
|
||||
QED_CHAIN_PAGE_SIZE,
|
||||
p_chain->p_virt_addr, p_chain->p_phys_addr);
|
||||
}
|
||||
|
||||
static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
|
||||
{
|
||||
void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
|
||||
u32 page_cnt = p_chain->page_cnt, i, pbl_size;
|
||||
u8 *p_pbl_virt = p_chain->pbl.p_virt_table;
|
||||
|
||||
if (!pp_virt_addr_tbl)
|
||||
return;
|
||||
|
||||
if (!p_chain->pbl.p_virt_table)
|
||||
goto out;
|
||||
|
||||
for (i = 0; i < page_cnt; i++) {
|
||||
if (!pp_virt_addr_tbl[i])
|
||||
break;
|
||||
|
||||
dma_free_coherent(&cdev->pdev->dev,
|
||||
QED_CHAIN_PAGE_SIZE,
|
||||
pp_virt_addr_tbl[i],
|
||||
*(dma_addr_t *)p_pbl_virt);
|
||||
|
||||
p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
|
||||
}
|
||||
|
||||
pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
|
||||
dma_free_coherent(&cdev->pdev->dev,
|
||||
pbl_size,
|
||||
p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table);
|
||||
out:
|
||||
vfree(p_chain->pbl.pp_virt_addr_tbl);
|
||||
}
|
||||
|
||||
void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
|
||||
{
|
||||
switch (p_chain->mode) {
|
||||
case QED_CHAIN_MODE_NEXT_PTR:
|
||||
qed_chain_free_next_ptr(cdev, p_chain);
|
||||
break;
|
||||
case QED_CHAIN_MODE_SINGLE:
|
||||
qed_chain_free_single(cdev, p_chain);
|
||||
break;
|
||||
case QED_CHAIN_MODE_PBL:
|
||||
qed_chain_free_pbl(cdev, p_chain);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
qed_chain_alloc_sanity_check(struct qed_dev *cdev,
|
||||
enum qed_chain_cnt_type cnt_type,
|
||||
size_t elem_size, u32 page_cnt)
|
||||
{
|
||||
u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
|
||||
|
||||
/* The actual chain size can be larger than the maximal possible value
|
||||
* after rounding up the requested elements number to pages, and after
|
||||
* taking into acount the unusuable elements (next-ptr elements).
|
||||
* The size of a "u16" chain can be (U16_MAX + 1) since the chain
|
||||
* size/capacity fields are of a u32 type.
|
||||
*/
|
||||
if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
|
||||
chain_size > 0x10000) ||
|
||||
(cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
|
||||
chain_size > 0x100000000ULL)) {
|
||||
DP_NOTICE(cdev,
|
||||
"The actual chain size (0x%llx) is larger than the maximal possible value\n",
|
||||
chain_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
|
||||
{
|
||||
void *p_virt = NULL, *p_virt_prev = NULL;
|
||||
dma_addr_t p_phys = 0;
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < p_chain->page_cnt; i++) {
|
||||
p_virt = dma_alloc_coherent(&cdev->pdev->dev,
|
||||
QED_CHAIN_PAGE_SIZE,
|
||||
&p_phys, GFP_KERNEL);
|
||||
if (!p_virt) {
|
||||
DP_NOTICE(cdev, "Failed to allocate chain memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (i == 0) {
|
||||
qed_chain_init_mem(p_chain, p_virt, p_phys);
|
||||
qed_chain_reset(p_chain);
|
||||
} else {
|
||||
qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
|
||||
p_virt, p_phys);
|
||||
}
|
||||
|
||||
p_virt_prev = p_virt;
|
||||
}
|
||||
/* Last page's next element should point to the beginning of the
|
||||
* chain.
|
||||
*/
|
||||
qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
|
||||
p_chain->p_virt_addr,
|
||||
p_chain->p_phys_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
|
||||
{
|
||||
dma_addr_t p_phys = 0;
|
||||
void *p_virt = NULL;
|
||||
|
||||
p_virt = dma_alloc_coherent(&cdev->pdev->dev,
|
||||
QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
|
||||
if (!p_virt) {
|
||||
DP_NOTICE(cdev, "Failed to allocate chain memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
qed_chain_init_mem(p_chain, p_virt, p_phys);
|
||||
qed_chain_reset(p_chain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
|
||||
{
|
||||
u32 page_cnt = p_chain->page_cnt, size, i;
|
||||
dma_addr_t p_phys = 0, p_pbl_phys = 0;
|
||||
void **pp_virt_addr_tbl = NULL;
|
||||
u8 *p_pbl_virt = NULL;
|
||||
void *p_virt = NULL;
|
||||
|
||||
size = page_cnt * sizeof(*pp_virt_addr_tbl);
|
||||
pp_virt_addr_tbl = vmalloc(size);
|
||||
if (!pp_virt_addr_tbl) {
|
||||
DP_NOTICE(cdev,
|
||||
"Failed to allocate memory for the chain virtual addresses table\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset(pp_virt_addr_tbl, 0, size);
|
||||
|
||||
/* The allocation of the PBL table is done with its full size, since it
|
||||
* is expected to be successive.
|
||||
* qed_chain_init_pbl_mem() is called even in a case of an allocation
|
||||
* failure, since pp_virt_addr_tbl was previously allocated, and it
|
||||
* should be saved to allow its freeing during the error flow.
|
||||
*/
|
||||
size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
|
||||
p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
|
||||
size, &p_pbl_phys, GFP_KERNEL);
|
||||
qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
|
||||
pp_virt_addr_tbl);
|
||||
if (!p_pbl_virt) {
|
||||
DP_NOTICE(cdev, "Failed to allocate chain pbl memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (i = 0; i < page_cnt; i++) {
|
||||
p_virt = dma_alloc_coherent(&cdev->pdev->dev,
|
||||
QED_CHAIN_PAGE_SIZE,
|
||||
&p_phys, GFP_KERNEL);
|
||||
if (!p_virt) {
|
||||
DP_NOTICE(cdev, "Failed to allocate chain memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (i == 0) {
|
||||
qed_chain_init_mem(p_chain, p_virt, p_phys);
|
||||
qed_chain_reset(p_chain);
|
||||
}
|
||||
|
||||
/* Fill the PBL table with the physical address of the page */
|
||||
*(dma_addr_t *)p_pbl_virt = p_phys;
|
||||
/* Keep the virtual address of the page */
|
||||
p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
|
||||
|
||||
p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int qed_chain_alloc(struct qed_dev *cdev,
|
||||
enum qed_chain_use_mode intended_use,
|
||||
enum qed_chain_mode mode,
|
||||
u16 num_elems,
|
||||
size_t elem_size,
|
||||
struct qed_chain *p_chain)
|
||||
enum qed_chain_cnt_type cnt_type,
|
||||
u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
|
||||
{
|
||||
dma_addr_t p_pbl_phys = 0;
|
||||
void *p_pbl_virt = NULL;
|
||||
dma_addr_t p_phys = 0;
|
||||
void *p_virt = NULL;
|
||||
u16 page_cnt = 0;
|
||||
size_t size;
|
||||
u32 page_cnt;
|
||||
int rc = 0;
|
||||
|
||||
if (mode == QED_CHAIN_MODE_SINGLE)
|
||||
page_cnt = 1;
|
||||
else
|
||||
page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
|
||||
|
||||
size = page_cnt * QED_CHAIN_PAGE_SIZE;
|
||||
p_virt = dma_alloc_coherent(&cdev->pdev->dev,
|
||||
size, &p_phys, GFP_KERNEL);
|
||||
if (!p_virt) {
|
||||
DP_NOTICE(cdev, "Failed to allocate chain mem\n");
|
||||
rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
|
||||
if (rc) {
|
||||
DP_NOTICE(cdev,
|
||||
"Cannot allocate a chain with the given arguments:\n"
|
||||
"[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
|
||||
intended_use, mode, cnt_type, num_elems, elem_size);
|
||||
return rc;
|
||||
}
|
||||
|
||||
qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
|
||||
mode, cnt_type);
|
||||
|
||||
switch (mode) {
|
||||
case QED_CHAIN_MODE_NEXT_PTR:
|
||||
rc = qed_chain_alloc_next_ptr(cdev, p_chain);
|
||||
break;
|
||||
case QED_CHAIN_MODE_SINGLE:
|
||||
rc = qed_chain_alloc_single(cdev, p_chain);
|
||||
break;
|
||||
case QED_CHAIN_MODE_PBL:
|
||||
rc = qed_chain_alloc_pbl(cdev, p_chain);
|
||||
break;
|
||||
}
|
||||
if (rc)
|
||||
goto nomem;
|
||||
}
|
||||
|
||||
if (mode == QED_CHAIN_MODE_PBL) {
|
||||
size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
|
||||
p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
|
||||
size, &p_pbl_phys,
|
||||
GFP_KERNEL);
|
||||
if (!p_pbl_virt) {
|
||||
DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n");
|
||||
goto nomem;
|
||||
}
|
||||
|
||||
qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt,
|
||||
(u8)elem_size, intended_use,
|
||||
p_pbl_phys, p_pbl_virt);
|
||||
} else {
|
||||
qed_chain_init(p_chain, p_virt, p_phys, page_cnt,
|
||||
(u8)elem_size, intended_use, mode);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
nomem:
|
||||
dma_free_coherent(&cdev->pdev->dev,
|
||||
page_cnt * QED_CHAIN_PAGE_SIZE,
|
||||
p_virt, p_phys);
|
||||
dma_free_coherent(&cdev->pdev->dev,
|
||||
page_cnt * QED_CHAIN_PBL_ENTRY_SIZE,
|
||||
p_pbl_virt, p_pbl_phys);
|
||||
|
||||
return -ENOMEM;
|
||||
qed_chain_free(cdev, p_chain);
|
||||
return rc;
|
||||
}
|
||||
|
||||
void qed_chain_free(struct qed_dev *cdev,
|
||||
struct qed_chain *p_chain)
|
||||
{
|
||||
size_t size;
|
||||
|
||||
if (!p_chain->p_virt_addr)
|
||||
return;
|
||||
|
||||
if (p_chain->mode == QED_CHAIN_MODE_PBL) {
|
||||
size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
|
||||
dma_free_coherent(&cdev->pdev->dev, size,
|
||||
p_chain->pbl.p_virt_table,
|
||||
p_chain->pbl.p_phys_table);
|
||||
}
|
||||
|
||||
size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE;
|
||||
dma_free_coherent(&cdev->pdev->dev, size,
|
||||
p_chain->p_virt_addr,
|
||||
p_chain->p_phys_addr);
|
||||
}
|
||||
|
||||
int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
|
||||
u16 src_id, u16 *dst_id)
|
||||
int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
|
||||
{
|
||||
if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
|
||||
u16 min, max;
|
||||
|
||||
min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
|
||||
min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
|
||||
max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
|
||||
DP_NOTICE(p_hwfn,
|
||||
"l2_queue id [%d] is not valid, available indices [%d - %d]\n",
|
||||
|
|
|
@ -245,9 +245,8 @@ int
|
|||
qed_chain_alloc(struct qed_dev *cdev,
|
||||
enum qed_chain_use_mode intended_use,
|
||||
enum qed_chain_mode mode,
|
||||
u16 num_elems,
|
||||
size_t elem_size,
|
||||
struct qed_chain *p_chain);
|
||||
enum qed_chain_cnt_type cnt_type,
|
||||
u32 num_elems, size_t elem_size, struct qed_chain *p_chain);
|
||||
|
||||
/**
|
||||
* @brief qed_chain_free - Free chain DMA memory
|
||||
|
@ -255,8 +254,7 @@ qed_chain_alloc(struct qed_dev *cdev,
|
|||
* @param p_hwfn
|
||||
* @param p_chain
|
||||
*/
|
||||
void qed_chain_free(struct qed_dev *cdev,
|
||||
struct qed_chain *p_chain);
|
||||
void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain);
|
||||
|
||||
/**
|
||||
* @@brief qed_fw_l2_queue - Get absolute L2 queue ID
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -791,16 +791,16 @@ qed_dmae_host2host(struct qed_hwfn *p_hwfn,
|
|||
}
|
||||
|
||||
u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
||||
enum protocol_type proto,
|
||||
union qed_qm_pq_params *p_params)
|
||||
enum protocol_type proto, union qed_qm_pq_params *p_params)
|
||||
{
|
||||
u16 pq_id = 0;
|
||||
|
||||
if ((proto == PROTOCOLID_CORE || proto == PROTOCOLID_ETH) &&
|
||||
!p_params) {
|
||||
if ((proto == PROTOCOLID_CORE ||
|
||||
proto == PROTOCOLID_ETH ||
|
||||
proto == PROTOCOLID_ISCSI ||
|
||||
proto == PROTOCOLID_ROCE) && !p_params) {
|
||||
DP_NOTICE(p_hwfn,
|
||||
"Protocol %d received NULL PQ params\n",
|
||||
proto);
|
||||
"Protocol %d received NULL PQ params\n", proto);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -808,6 +808,8 @@ u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
|||
case PROTOCOLID_CORE:
|
||||
if (p_params->core.tc == LB_TC)
|
||||
pq_id = p_hwfn->qm_info.pure_lb_pq;
|
||||
else if (p_params->core.tc == OOO_LB_TC)
|
||||
pq_id = p_hwfn->qm_info.ooo_pq;
|
||||
else
|
||||
pq_id = p_hwfn->qm_info.offload_pq;
|
||||
break;
|
||||
|
@ -817,6 +819,18 @@ u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
|||
pq_id += p_hwfn->qm_info.vf_queues_offset +
|
||||
p_params->eth.vf_id;
|
||||
break;
|
||||
case PROTOCOLID_ISCSI:
|
||||
if (p_params->iscsi.q_idx == 1)
|
||||
pq_id = p_hwfn->qm_info.pure_ack_pq;
|
||||
break;
|
||||
case PROTOCOLID_ROCE:
|
||||
if (p_params->roce.dcqcn)
|
||||
pq_id = p_params->roce.qpid;
|
||||
else
|
||||
pq_id = p_hwfn->qm_info.offload_pq;
|
||||
if (pq_id > p_hwfn->qm_info.num_pf_rls)
|
||||
pq_id = p_hwfn->qm_info.offload_pq;
|
||||
break;
|
||||
default:
|
||||
pq_id = 0;
|
||||
}
|
||||
|
|
|
@ -253,6 +253,10 @@ int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn);
|
|||
void qed_dmae_info_free(struct qed_hwfn *p_hwfn);
|
||||
|
||||
union qed_qm_pq_params {
|
||||
struct {
|
||||
u8 q_idx;
|
||||
} iscsi;
|
||||
|
||||
struct {
|
||||
u8 tc;
|
||||
} core;
|
||||
|
@ -262,11 +266,15 @@ union qed_qm_pq_params {
|
|||
u8 vf_id;
|
||||
u8 tc;
|
||||
} eth;
|
||||
|
||||
struct {
|
||||
u8 dcqcn;
|
||||
u8 qpid; /* roce relative */
|
||||
} roce;
|
||||
};
|
||||
|
||||
u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
||||
enum protocol_type proto,
|
||||
union qed_qm_pq_params *params);
|
||||
enum protocol_type proto, union qed_qm_pq_params *params);
|
||||
|
||||
int qed_init_fw_data(struct qed_dev *cdev,
|
||||
const u8 *fw_data);
|
||||
|
|
|
@ -207,6 +207,8 @@ int qed_fill_dev_info(struct qed_dev *cdev,
|
|||
dev_info->pci_mem_start = cdev->pci_params.mem_start;
|
||||
dev_info->pci_mem_end = cdev->pci_params.mem_end;
|
||||
dev_info->pci_irq = cdev->pci_params.irq;
|
||||
dev_info->rdma_supported =
|
||||
(cdev->hwfns[0].hw_info.personality == QED_PCI_ETH_ROCE);
|
||||
dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
|
||||
ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
|
||||
|
||||
|
@ -901,7 +903,8 @@ static int qed_slowpath_stop(struct qed_dev *cdev)
|
|||
|
||||
if (IS_PF(cdev)) {
|
||||
qed_free_stream_mem(cdev);
|
||||
qed_sriov_disable(cdev, true);
|
||||
if (IS_QED_ETH_IF(cdev))
|
||||
qed_sriov_disable(cdev, true);
|
||||
|
||||
qed_nic_stop(cdev);
|
||||
qed_slowpath_irq_free(cdev);
|
||||
|
|
|
@ -977,7 +977,18 @@ qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
|
|||
|
||||
switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
|
||||
case FUNC_MF_CFG_PROTOCOL_ETHERNET:
|
||||
*p_proto = QED_PCI_ETH;
|
||||
if (test_bit(QED_DEV_CAP_ROCE,
|
||||
&p_hwfn->hw_info.device_capabilities))
|
||||
*p_proto = QED_PCI_ETH_ROCE;
|
||||
else
|
||||
*p_proto = QED_PCI_ETH;
|
||||
break;
|
||||
case FUNC_MF_CFG_PROTOCOL_ISCSI:
|
||||
*p_proto = QED_PCI_ISCSI;
|
||||
break;
|
||||
case FUNC_MF_CFG_PROTOCOL_ROCE:
|
||||
DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
|
||||
rc = -EINVAL;
|
||||
break;
|
||||
default:
|
||||
rc = -EINVAL;
|
||||
|
|
|
@ -27,6 +27,35 @@
|
|||
#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
|
||||
0xff << 24)
|
||||
|
||||
#define CDU_REG_SEGMENT0_PARAMS \
|
||||
0x580904UL
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
|
||||
(0xfff << 0)
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
|
||||
0
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
|
||||
(0xff << 16)
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
|
||||
16
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
|
||||
(0xff << 24)
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
|
||||
24
|
||||
#define CDU_REG_SEGMENT1_PARAMS \
|
||||
0x580908UL
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
|
||||
(0xfff << 0)
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
|
||||
0
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
|
||||
(0xff << 16)
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
|
||||
16
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
|
||||
(0xff << 24)
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
|
||||
24
|
||||
|
||||
#define XSDM_REG_OPERATION_GEN \
|
||||
0xf80408UL
|
||||
#define NIG_REG_RX_BRB_OUT_EN \
|
||||
|
@ -225,6 +254,8 @@
|
|||
0x1f0000UL
|
||||
#define PRS_REG_MSG_INFO \
|
||||
0x1f0a1cUL
|
||||
#define PRS_REG_ROCE_DEST_QP_MAX_PF \
|
||||
0x1f0430UL
|
||||
#define PSDM_REG_ENABLE_IN1 \
|
||||
0xfa0004UL
|
||||
#define PSEM_REG_ENABLE_IN \
|
||||
|
@ -233,6 +264,8 @@
|
|||
0x280020UL
|
||||
#define PSWRQ2_REG_CDUT_P_SIZE \
|
||||
0x24000cUL
|
||||
#define PSWRQ2_REG_ILT_MEMORY \
|
||||
0x260000UL
|
||||
#define PSWHST_REG_DISCARD_INTERNAL_WRITES \
|
||||
0x2a0040UL
|
||||
#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
|
||||
|
|
|
@ -63,6 +63,32 @@ union ramrod_data {
|
|||
struct vport_update_ramrod_data vport_update;
|
||||
struct vport_filter_update_ramrod_data vport_filter_update;
|
||||
|
||||
struct rdma_init_func_ramrod_data rdma_init_func;
|
||||
struct rdma_close_func_ramrod_data rdma_close_func;
|
||||
struct rdma_register_tid_ramrod_data rdma_register_tid;
|
||||
struct rdma_deregister_tid_ramrod_data rdma_deregister_tid;
|
||||
struct roce_create_qp_resp_ramrod_data roce_create_qp_resp;
|
||||
struct roce_create_qp_req_ramrod_data roce_create_qp_req;
|
||||
struct roce_modify_qp_resp_ramrod_data roce_modify_qp_resp;
|
||||
struct roce_modify_qp_req_ramrod_data roce_modify_qp_req;
|
||||
struct roce_query_qp_resp_ramrod_data roce_query_qp_resp;
|
||||
struct roce_query_qp_req_ramrod_data roce_query_qp_req;
|
||||
struct roce_destroy_qp_resp_ramrod_data roce_destroy_qp_resp;
|
||||
struct roce_destroy_qp_req_ramrod_data roce_destroy_qp_req;
|
||||
struct rdma_create_cq_ramrod_data rdma_create_cq;
|
||||
struct rdma_resize_cq_ramrod_data rdma_resize_cq;
|
||||
struct rdma_destroy_cq_ramrod_data rdma_destroy_cq;
|
||||
struct rdma_srq_create_ramrod_data rdma_create_srq;
|
||||
struct rdma_srq_destroy_ramrod_data rdma_destroy_srq;
|
||||
struct rdma_srq_modify_ramrod_data rdma_modify_srq;
|
||||
|
||||
struct iscsi_slow_path_hdr iscsi_empty;
|
||||
struct iscsi_init_ramrod_params iscsi_init;
|
||||
struct iscsi_spe_func_dstry iscsi_destroy;
|
||||
struct iscsi_spe_conn_offload iscsi_conn_offload;
|
||||
struct iscsi_conn_update_ramrod_params iscsi_conn_update;
|
||||
struct iscsi_spe_conn_termination iscsi_conn_terminate;
|
||||
|
||||
struct vf_start_ramrod_data vf_start;
|
||||
struct vf_stop_ramrod_data vf_stop;
|
||||
};
|
||||
|
|
|
@ -308,6 +308,7 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
|
|||
struct qed_spq_entry *p_ent = NULL;
|
||||
struct qed_sp_init_data init_data;
|
||||
int rc = -EINVAL;
|
||||
u8 page_cnt;
|
||||
|
||||
/* update initial eq producer */
|
||||
qed_eq_prod_update(p_hwfn,
|
||||
|
@ -350,18 +351,33 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
|
|||
/* Place EQ address in RAMROD */
|
||||
DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
|
||||
p_hwfn->p_eq->chain.pbl.p_phys_table);
|
||||
p_ramrod->event_ring_num_pages = (u8)p_hwfn->p_eq->chain.page_cnt;
|
||||
|
||||
page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
|
||||
p_ramrod->event_ring_num_pages = page_cnt;
|
||||
DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
|
||||
p_hwfn->p_consq->chain.pbl.p_phys_table);
|
||||
|
||||
qed_tunn_set_pf_start_params(p_hwfn, p_tunn,
|
||||
&p_ramrod->tunnel_config);
|
||||
p_hwfn->hw_info.personality = PERSONALITY_ETH;
|
||||
|
||||
if (IS_MF_SI(p_hwfn))
|
||||
p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
|
||||
|
||||
switch (p_hwfn->hw_info.personality) {
|
||||
case QED_PCI_ETH:
|
||||
p_ramrod->personality = PERSONALITY_ETH;
|
||||
break;
|
||||
case QED_PCI_ISCSI:
|
||||
p_ramrod->personality = PERSONALITY_ISCSI;
|
||||
break;
|
||||
case QED_PCI_ETH_ROCE:
|
||||
p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
|
||||
break;
|
||||
default:
|
||||
DP_NOTICE(p_hwfn, "Unkown personality %d\n",
|
||||
p_hwfn->hw_info.personality);
|
||||
p_ramrod->personality = PERSONALITY_ETH;
|
||||
}
|
||||
|
||||
if (p_hwfn->cdev->p_iov_info) {
|
||||
struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
|
||||
|
||||
|
|
|
@ -343,6 +343,7 @@ struct qed_eq *qed_eq_alloc(struct qed_hwfn *p_hwfn,
|
|||
if (qed_chain_alloc(p_hwfn->cdev,
|
||||
QED_CHAIN_USE_TO_PRODUCE,
|
||||
QED_CHAIN_MODE_PBL,
|
||||
QED_CHAIN_CNT_TYPE_U16,
|
||||
num_elem,
|
||||
sizeof(union event_ring_element),
|
||||
&p_eq->chain)) {
|
||||
|
@ -416,10 +417,10 @@ int qed_eth_cqe_completion(struct qed_hwfn *p_hwfn,
|
|||
***************************************************************************/
|
||||
void qed_spq_setup(struct qed_hwfn *p_hwfn)
|
||||
{
|
||||
struct qed_spq *p_spq = p_hwfn->p_spq;
|
||||
struct qed_spq_entry *p_virt = NULL;
|
||||
dma_addr_t p_phys = 0;
|
||||
unsigned int i = 0;
|
||||
struct qed_spq *p_spq = p_hwfn->p_spq;
|
||||
struct qed_spq_entry *p_virt = NULL;
|
||||
dma_addr_t p_phys = 0;
|
||||
u32 i, capacity;
|
||||
|
||||
INIT_LIST_HEAD(&p_spq->pending);
|
||||
INIT_LIST_HEAD(&p_spq->completion_pending);
|
||||
|
@ -431,7 +432,8 @@ void qed_spq_setup(struct qed_hwfn *p_hwfn)
|
|||
p_phys = p_spq->p_phys + offsetof(struct qed_spq_entry, ramrod);
|
||||
p_virt = p_spq->p_virt;
|
||||
|
||||
for (i = 0; i < p_spq->chain.capacity; i++) {
|
||||
capacity = qed_chain_get_capacity(&p_spq->chain);
|
||||
for (i = 0; i < capacity; i++) {
|
||||
DMA_REGPAIR_LE(p_virt->elem.data_ptr, p_phys);
|
||||
|
||||
list_add_tail(&p_virt->list, &p_spq->free_pool);
|
||||
|
@ -459,9 +461,10 @@ void qed_spq_setup(struct qed_hwfn *p_hwfn)
|
|||
|
||||
int qed_spq_alloc(struct qed_hwfn *p_hwfn)
|
||||
{
|
||||
struct qed_spq *p_spq = NULL;
|
||||
dma_addr_t p_phys = 0;
|
||||
struct qed_spq_entry *p_virt = NULL;
|
||||
struct qed_spq_entry *p_virt = NULL;
|
||||
struct qed_spq *p_spq = NULL;
|
||||
dma_addr_t p_phys = 0;
|
||||
u32 capacity;
|
||||
|
||||
/* SPQ struct */
|
||||
p_spq =
|
||||
|
@ -475,6 +478,7 @@ int qed_spq_alloc(struct qed_hwfn *p_hwfn)
|
|||
if (qed_chain_alloc(p_hwfn->cdev,
|
||||
QED_CHAIN_USE_TO_PRODUCE,
|
||||
QED_CHAIN_MODE_SINGLE,
|
||||
QED_CHAIN_CNT_TYPE_U16,
|
||||
0, /* N/A when the mode is SINGLE */
|
||||
sizeof(struct slow_path_element),
|
||||
&p_spq->chain)) {
|
||||
|
@ -483,11 +487,11 @@ int qed_spq_alloc(struct qed_hwfn *p_hwfn)
|
|||
}
|
||||
|
||||
/* allocate and fill the SPQ elements (incl. ramrod data list) */
|
||||
capacity = qed_chain_get_capacity(&p_spq->chain);
|
||||
p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
|
||||
p_spq->chain.capacity *
|
||||
capacity *
|
||||
sizeof(struct qed_spq_entry),
|
||||
&p_phys,
|
||||
GFP_KERNEL);
|
||||
&p_phys, GFP_KERNEL);
|
||||
|
||||
if (!p_virt)
|
||||
goto spq_allocate_fail;
|
||||
|
@ -507,16 +511,18 @@ spq_allocate_fail:
|
|||
void qed_spq_free(struct qed_hwfn *p_hwfn)
|
||||
{
|
||||
struct qed_spq *p_spq = p_hwfn->p_spq;
|
||||
u32 capacity;
|
||||
|
||||
if (!p_spq)
|
||||
return;
|
||||
|
||||
if (p_spq->p_virt)
|
||||
if (p_spq->p_virt) {
|
||||
capacity = qed_chain_get_capacity(&p_spq->chain);
|
||||
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
|
||||
p_spq->chain.capacity *
|
||||
capacity *
|
||||
sizeof(struct qed_spq_entry),
|
||||
p_spq->p_virt,
|
||||
p_spq->p_phys);
|
||||
p_spq->p_virt, p_spq->p_phys);
|
||||
}
|
||||
|
||||
qed_chain_free(p_hwfn->cdev, &p_spq->chain);
|
||||
;
|
||||
|
@ -871,9 +877,9 @@ struct qed_consq *qed_consq_alloc(struct qed_hwfn *p_hwfn)
|
|||
if (qed_chain_alloc(p_hwfn->cdev,
|
||||
QED_CHAIN_USE_TO_PRODUCE,
|
||||
QED_CHAIN_MODE_PBL,
|
||||
QED_CHAIN_CNT_TYPE_U16,
|
||||
QED_CHAIN_PAGE_SIZE / 0x80,
|
||||
0x80,
|
||||
&p_consq->chain)) {
|
||||
0x80, &p_consq->chain)) {
|
||||
DP_NOTICE(p_hwfn, "Failed to allocate consq chain");
|
||||
goto consq_allocate_fail;
|
||||
}
|
||||
|
|
|
@ -2817,6 +2817,7 @@ static int qede_alloc_mem_rxq(struct qede_dev *edev,
|
|||
rc = edev->ops->common->chain_alloc(edev->cdev,
|
||||
QED_CHAIN_USE_TO_CONSUME_PRODUCE,
|
||||
QED_CHAIN_MODE_NEXT_PTR,
|
||||
QED_CHAIN_CNT_TYPE_U16,
|
||||
RX_RING_SIZE,
|
||||
sizeof(struct eth_rx_bd),
|
||||
&rxq->rx_bd_ring);
|
||||
|
@ -2828,6 +2829,7 @@ static int qede_alloc_mem_rxq(struct qede_dev *edev,
|
|||
rc = edev->ops->common->chain_alloc(edev->cdev,
|
||||
QED_CHAIN_USE_TO_CONSUME,
|
||||
QED_CHAIN_MODE_PBL,
|
||||
QED_CHAIN_CNT_TYPE_U16,
|
||||
RX_RING_SIZE,
|
||||
sizeof(union eth_rx_cqe),
|
||||
&rxq->rx_comp_ring);
|
||||
|
@ -2879,9 +2881,9 @@ static int qede_alloc_mem_txq(struct qede_dev *edev,
|
|||
rc = edev->ops->common->chain_alloc(edev->cdev,
|
||||
QED_CHAIN_USE_TO_CONSUME_PRODUCE,
|
||||
QED_CHAIN_MODE_PBL,
|
||||
QED_CHAIN_CNT_TYPE_U16,
|
||||
NUM_TX_BDS_MAX,
|
||||
sizeof(*p_virt),
|
||||
&txq->tx_pbl);
|
||||
sizeof(*p_virt), &txq->tx_pbl);
|
||||
if (rc)
|
||||
goto err;
|
||||
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
#define CORE_SPQE_PAGE_SIZE_BYTES 4096
|
||||
|
||||
#define X_FINAL_CLEANUP_AGG_INT 1
|
||||
#define NUM_OF_GLOBAL_QUEUES 128
|
||||
|
||||
/* Queue Zone sizes in bytes */
|
||||
#define TSTORM_QZONE_SIZE 8
|
||||
|
@ -516,9 +517,9 @@ enum mf_mode {
|
|||
|
||||
/* Per-protocol connection types */
|
||||
enum protocol_type {
|
||||
PROTOCOLID_RESERVED1,
|
||||
PROTOCOLID_ISCSI,
|
||||
PROTOCOLID_RESERVED2,
|
||||
PROTOCOLID_RESERVED3,
|
||||
PROTOCOLID_ROCE,
|
||||
PROTOCOLID_CORE,
|
||||
PROTOCOLID_ETH,
|
||||
PROTOCOLID_RESERVED4,
|
||||
|
@ -694,7 +695,10 @@ struct parsing_and_err_flags {
|
|||
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
|
||||
};
|
||||
|
||||
/* Concrete Function ID. */
|
||||
struct pb_context {
|
||||
__le32 crc[4];
|
||||
};
|
||||
|
||||
struct pxp_concrete_fid {
|
||||
__le16 fid;
|
||||
#define PXP_CONCRETE_FID_PFID_MASK 0xF
|
||||
|
@ -761,6 +765,72 @@ struct pxp_ptt_entry {
|
|||
};
|
||||
|
||||
/* RSS hash type */
|
||||
struct rdif_task_context {
|
||||
__le32 initial_ref_tag;
|
||||
__le16 app_tag_value;
|
||||
__le16 app_tag_mask;
|
||||
u8 flags0;
|
||||
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
|
||||
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
|
||||
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
|
||||
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
|
||||
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
|
||||
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
|
||||
#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
|
||||
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
|
||||
u8 partial_dif_data[7];
|
||||
__le16 partial_crc_value;
|
||||
__le16 partial_checksum_value;
|
||||
__le32 offset_in_io;
|
||||
__le16 flags1;
|
||||
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
|
||||
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
|
||||
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
|
||||
#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
|
||||
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
|
||||
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
|
||||
#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
|
||||
#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
|
||||
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
|
||||
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
|
||||
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
|
||||
#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
|
||||
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
|
||||
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
|
||||
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
|
||||
__le16 state;
|
||||
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
|
||||
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
|
||||
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
|
||||
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
|
||||
#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
|
||||
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
|
||||
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
|
||||
#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
|
||||
#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
|
||||
#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
|
||||
#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
|
||||
__le32 reserved2;
|
||||
};
|
||||
|
||||
enum rss_hash_type {
|
||||
RSS_HASH_TYPE_DEFAULT = 0,
|
||||
RSS_HASH_TYPE_IPV4 = 1,
|
||||
|
@ -789,4 +859,122 @@ struct status_block {
|
|||
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
|
||||
};
|
||||
|
||||
struct tdif_task_context {
|
||||
__le32 initial_ref_tag;
|
||||
__le16 app_tag_value;
|
||||
__le16 app_tag_mask;
|
||||
__le16 partial_crc_valueB;
|
||||
__le16 partial_checksum_valueB;
|
||||
__le16 stateB;
|
||||
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
|
||||
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
|
||||
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
|
||||
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
|
||||
#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
|
||||
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
|
||||
#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
|
||||
#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
|
||||
u8 reserved1;
|
||||
u8 flags0;
|
||||
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
|
||||
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
|
||||
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
|
||||
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
|
||||
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
|
||||
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
|
||||
#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
|
||||
#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
|
||||
__le32 flags1;
|
||||
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
|
||||
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
|
||||
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
|
||||
#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
|
||||
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
|
||||
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
|
||||
#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
|
||||
#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
|
||||
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
|
||||
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
|
||||
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
|
||||
#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
|
||||
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
|
||||
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
|
||||
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
|
||||
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
|
||||
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
|
||||
#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
|
||||
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
|
||||
#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
|
||||
#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
|
||||
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
|
||||
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
|
||||
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
|
||||
#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
|
||||
#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
|
||||
__le32 offset_in_iob;
|
||||
__le16 partial_crc_value_a;
|
||||
__le16 partial_checksum_valuea_;
|
||||
__le32 offset_in_ioa;
|
||||
u8 partial_dif_data_a[8];
|
||||
u8 partial_dif_data_b[8];
|
||||
};
|
||||
|
||||
struct timers_context {
|
||||
__le32 logical_client0;
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
|
||||
#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
|
||||
#define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
|
||||
#define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
|
||||
#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
|
||||
#define TIMERS_CONTEXT_RESERVED0_MASK 0x3
|
||||
#define TIMERS_CONTEXT_RESERVED0_SHIFT 30
|
||||
__le32 logical_client1;
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
|
||||
#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
|
||||
#define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
|
||||
#define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
|
||||
#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
|
||||
#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
|
||||
#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
|
||||
__le32 logical_client2;
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
|
||||
#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
|
||||
#define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
|
||||
#define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
|
||||
#define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
|
||||
#define TIMERS_CONTEXT_RESERVED2_MASK 0x3
|
||||
#define TIMERS_CONTEXT_RESERVED2_SHIFT 30
|
||||
__le32 host_expiration_fields;
|
||||
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF
|
||||
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
|
||||
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
|
||||
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
|
||||
#define TIMERS_CONTEXT_RESERVED3_MASK 0x7
|
||||
#define TIMERS_CONTEXT_RESERVED3_SHIFT 29
|
||||
};
|
||||
#endif /* __COMMON_HSI__ */
|
||||
|
|
1439
include/linux/qed/iscsi_common.h
Normal file
1439
include/linux/qed/iscsi_common.h
Normal file
File diff suppressed because it is too large
Load diff
|
@ -47,16 +47,56 @@ enum qed_chain_use_mode {
|
|||
QED_CHAIN_USE_TO_CONSUME_PRODUCE, /* Chain starts empty */
|
||||
};
|
||||
|
||||
enum qed_chain_cnt_type {
|
||||
/* The chain's size/prod/cons are kept in 16-bit variables */
|
||||
QED_CHAIN_CNT_TYPE_U16,
|
||||
|
||||
/* The chain's size/prod/cons are kept in 32-bit variables */
|
||||
QED_CHAIN_CNT_TYPE_U32,
|
||||
};
|
||||
|
||||
struct qed_chain_next {
|
||||
struct regpair next_phys;
|
||||
void *next_virt;
|
||||
};
|
||||
|
||||
struct qed_chain_pbl_u16 {
|
||||
u16 prod_page_idx;
|
||||
u16 cons_page_idx;
|
||||
};
|
||||
|
||||
struct qed_chain_pbl_u32 {
|
||||
u32 prod_page_idx;
|
||||
u32 cons_page_idx;
|
||||
};
|
||||
|
||||
struct qed_chain_pbl {
|
||||
/* Base address of a pre-allocated buffer for pbl */
|
||||
dma_addr_t p_phys_table;
|
||||
void *p_virt_table;
|
||||
u16 prod_page_idx;
|
||||
u16 cons_page_idx;
|
||||
|
||||
/* Table for keeping the virtual addresses of the chain pages,
|
||||
* respectively to the physical addresses in the pbl table.
|
||||
*/
|
||||
void **pp_virt_addr_tbl;
|
||||
|
||||
/* Index to current used page by producer/consumer */
|
||||
union {
|
||||
struct qed_chain_pbl_u16 pbl16;
|
||||
struct qed_chain_pbl_u32 pbl32;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct qed_chain_u16 {
|
||||
/* Cyclic index of next element to produce/consme */
|
||||
u16 prod_idx;
|
||||
u16 cons_idx;
|
||||
};
|
||||
|
||||
struct qed_chain_u32 {
|
||||
/* Cyclic index of next element to produce/consme */
|
||||
u32 prod_idx;
|
||||
u32 cons_idx;
|
||||
};
|
||||
|
||||
struct qed_chain {
|
||||
|
@ -64,13 +104,25 @@ struct qed_chain {
|
|||
dma_addr_t p_phys_addr;
|
||||
void *p_prod_elem;
|
||||
void *p_cons_elem;
|
||||
u16 page_cnt;
|
||||
|
||||
enum qed_chain_mode mode;
|
||||
enum qed_chain_use_mode intended_use; /* used to produce/consume */
|
||||
u16 capacity; /*< number of _usable_ elements */
|
||||
u16 size; /* number of elements */
|
||||
u16 prod_idx;
|
||||
u16 cons_idx;
|
||||
enum qed_chain_cnt_type cnt_type;
|
||||
|
||||
union {
|
||||
struct qed_chain_u16 chain16;
|
||||
struct qed_chain_u32 chain32;
|
||||
} u;
|
||||
|
||||
u32 page_cnt;
|
||||
|
||||
/* Number of elements - capacity is for usable elements only,
|
||||
* while size will contain total number of elements [for entire chain].
|
||||
*/
|
||||
u32 capacity;
|
||||
u32 size;
|
||||
|
||||
/* Elements information for fast calculations */
|
||||
u16 elem_per_page;
|
||||
u16 elem_per_page_mask;
|
||||
u16 elem_unusable;
|
||||
|
@ -96,66 +148,69 @@ struct qed_chain {
|
|||
#define QED_CHAIN_PAGE_CNT(elem_cnt, elem_size, mode) \
|
||||
DIV_ROUND_UP(elem_cnt, USABLE_ELEMS_PER_PAGE(elem_size, mode))
|
||||
|
||||
#define is_chain_u16(p) ((p)->cnt_type == QED_CHAIN_CNT_TYPE_U16)
|
||||
#define is_chain_u32(p) ((p)->cnt_type == QED_CHAIN_CNT_TYPE_U32)
|
||||
|
||||
/* Accessors */
|
||||
static inline u16 qed_chain_get_prod_idx(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->prod_idx;
|
||||
return p_chain->u.chain16.prod_idx;
|
||||
}
|
||||
|
||||
static inline u16 qed_chain_get_cons_idx(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->cons_idx;
|
||||
return p_chain->u.chain16.cons_idx;
|
||||
}
|
||||
|
||||
static inline u32 qed_chain_get_cons_idx_u32(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->u.chain32.cons_idx;
|
||||
}
|
||||
|
||||
static inline u16 qed_chain_get_elem_left(struct qed_chain *p_chain)
|
||||
{
|
||||
u16 used;
|
||||
|
||||
/* we don't need to trancate upon assignmet, as we assign u32->u16 */
|
||||
used = ((u32)0x10000u + (u32)(p_chain->prod_idx)) -
|
||||
(u32)p_chain->cons_idx;
|
||||
used = (u16) (((u32)0x10000 +
|
||||
(u32)p_chain->u.chain16.prod_idx) -
|
||||
(u32)p_chain->u.chain16.cons_idx);
|
||||
if (p_chain->mode == QED_CHAIN_MODE_NEXT_PTR)
|
||||
used -= p_chain->prod_idx / p_chain->elem_per_page -
|
||||
p_chain->cons_idx / p_chain->elem_per_page;
|
||||
used -= p_chain->u.chain16.prod_idx / p_chain->elem_per_page -
|
||||
p_chain->u.chain16.cons_idx / p_chain->elem_per_page;
|
||||
|
||||
return (u16)(p_chain->capacity - used);
|
||||
}
|
||||
|
||||
static inline u32 qed_chain_get_elem_left_u32(struct qed_chain *p_chain)
|
||||
{
|
||||
u32 used;
|
||||
|
||||
used = (u32) (((u64)0x100000000ULL +
|
||||
(u64)p_chain->u.chain32.prod_idx) -
|
||||
(u64)p_chain->u.chain32.cons_idx);
|
||||
if (p_chain->mode == QED_CHAIN_MODE_NEXT_PTR)
|
||||
used -= p_chain->u.chain32.prod_idx / p_chain->elem_per_page -
|
||||
p_chain->u.chain32.cons_idx / p_chain->elem_per_page;
|
||||
|
||||
return p_chain->capacity - used;
|
||||
}
|
||||
|
||||
static inline u8 qed_chain_is_full(struct qed_chain *p_chain)
|
||||
{
|
||||
return qed_chain_get_elem_left(p_chain) == p_chain->capacity;
|
||||
}
|
||||
|
||||
static inline u8 qed_chain_is_empty(struct qed_chain *p_chain)
|
||||
{
|
||||
return qed_chain_get_elem_left(p_chain) == 0;
|
||||
}
|
||||
|
||||
static inline u16 qed_chain_get_elem_per_page(
|
||||
struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->elem_per_page;
|
||||
}
|
||||
|
||||
static inline u16 qed_chain_get_usable_per_page(
|
||||
struct qed_chain *p_chain)
|
||||
static inline u16 qed_chain_get_usable_per_page(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->usable_per_page;
|
||||
}
|
||||
|
||||
static inline u16 qed_chain_get_unusable_per_page(
|
||||
struct qed_chain *p_chain)
|
||||
static inline u16 qed_chain_get_unusable_per_page(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->elem_unusable;
|
||||
}
|
||||
|
||||
static inline u16 qed_chain_get_size(struct qed_chain *p_chain)
|
||||
static inline u32 qed_chain_get_page_cnt(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->size;
|
||||
return p_chain->page_cnt;
|
||||
}
|
||||
|
||||
static inline dma_addr_t
|
||||
qed_chain_get_pbl_phys(struct qed_chain *p_chain)
|
||||
static inline dma_addr_t qed_chain_get_pbl_phys(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->pbl.p_phys_table;
|
||||
}
|
||||
|
@ -172,64 +227,62 @@ qed_chain_get_pbl_phys(struct qed_chain *p_chain)
|
|||
*/
|
||||
static inline void
|
||||
qed_chain_advance_page(struct qed_chain *p_chain,
|
||||
void **p_next_elem,
|
||||
u16 *idx_to_inc,
|
||||
u16 *page_to_inc)
|
||||
void **p_next_elem, void *idx_to_inc, void *page_to_inc)
|
||||
|
||||
{
|
||||
struct qed_chain_next *p_next = NULL;
|
||||
u32 page_index = 0;
|
||||
switch (p_chain->mode) {
|
||||
case QED_CHAIN_MODE_NEXT_PTR:
|
||||
{
|
||||
struct qed_chain_next *p_next = *p_next_elem;
|
||||
p_next = *p_next_elem;
|
||||
*p_next_elem = p_next->next_virt;
|
||||
*idx_to_inc += p_chain->elem_unusable;
|
||||
if (is_chain_u16(p_chain))
|
||||
*(u16 *)idx_to_inc += p_chain->elem_unusable;
|
||||
else
|
||||
*(u32 *)idx_to_inc += p_chain->elem_unusable;
|
||||
break;
|
||||
}
|
||||
case QED_CHAIN_MODE_SINGLE:
|
||||
*p_next_elem = p_chain->p_virt_addr;
|
||||
break;
|
||||
|
||||
case QED_CHAIN_MODE_PBL:
|
||||
/* It is assumed pages are sequential, next element needs
|
||||
* to change only when passing going back to first from last.
|
||||
*/
|
||||
if (++(*page_to_inc) == p_chain->page_cnt) {
|
||||
*page_to_inc = 0;
|
||||
*p_next_elem = p_chain->p_virt_addr;
|
||||
if (is_chain_u16(p_chain)) {
|
||||
if (++(*(u16 *)page_to_inc) == p_chain->page_cnt)
|
||||
*(u16 *)page_to_inc = 0;
|
||||
page_index = *(u16 *)page_to_inc;
|
||||
} else {
|
||||
if (++(*(u32 *)page_to_inc) == p_chain->page_cnt)
|
||||
*(u32 *)page_to_inc = 0;
|
||||
page_index = *(u32 *)page_to_inc;
|
||||
}
|
||||
*p_next_elem = p_chain->pbl.pp_virt_addr_tbl[page_index];
|
||||
}
|
||||
}
|
||||
|
||||
#define is_unusable_idx(p, idx) \
|
||||
(((p)->idx & (p)->elem_per_page_mask) == (p)->usable_per_page)
|
||||
(((p)->u.chain16.idx & (p)->elem_per_page_mask) == (p)->usable_per_page)
|
||||
|
||||
#define is_unusable_next_idx(p, idx) \
|
||||
((((p)->idx + 1) & (p)->elem_per_page_mask) == (p)->usable_per_page)
|
||||
#define is_unusable_idx_u32(p, idx) \
|
||||
(((p)->u.chain32.idx & (p)->elem_per_page_mask) == (p)->usable_per_page)
|
||||
#define is_unusable_next_idx(p, idx) \
|
||||
((((p)->u.chain16.idx + 1) & (p)->elem_per_page_mask) == \
|
||||
(p)->usable_per_page)
|
||||
|
||||
#define test_ans_skip(p, idx) \
|
||||
#define is_unusable_next_idx_u32(p, idx) \
|
||||
((((p)->u.chain32.idx + 1) & (p)->elem_per_page_mask) == \
|
||||
(p)->usable_per_page)
|
||||
|
||||
#define test_and_skip(p, idx) \
|
||||
do { \
|
||||
if (is_unusable_idx(p, idx)) { \
|
||||
(p)->idx += (p)->elem_unusable; \
|
||||
if (is_chain_u16(p)) { \
|
||||
if (is_unusable_idx(p, idx)) \
|
||||
(p)->u.chain16.idx += (p)->elem_unusable; \
|
||||
} else { \
|
||||
if (is_unusable_idx_u32(p, idx)) \
|
||||
(p)->u.chain32.idx += (p)->elem_unusable; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief qed_chain_return_multi_produced -
|
||||
*
|
||||
* A chain in which the driver "Produces" elements should use this API
|
||||
* to indicate previous produced elements are now consumed.
|
||||
*
|
||||
* @param p_chain
|
||||
* @param num
|
||||
*/
|
||||
static inline void
|
||||
qed_chain_return_multi_produced(struct qed_chain *p_chain,
|
||||
u16 num)
|
||||
{
|
||||
p_chain->cons_idx += num;
|
||||
test_ans_skip(p_chain, cons_idx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_return_produced -
|
||||
*
|
||||
|
@ -240,8 +293,11 @@ qed_chain_return_multi_produced(struct qed_chain *p_chain,
|
|||
*/
|
||||
static inline void qed_chain_return_produced(struct qed_chain *p_chain)
|
||||
{
|
||||
p_chain->cons_idx++;
|
||||
test_ans_skip(p_chain, cons_idx);
|
||||
if (is_chain_u16(p_chain))
|
||||
p_chain->u.chain16.cons_idx++;
|
||||
else
|
||||
p_chain->u.chain32.cons_idx++;
|
||||
test_and_skip(p_chain, cons_idx);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -257,21 +313,33 @@ static inline void qed_chain_return_produced(struct qed_chain *p_chain)
|
|||
*/
|
||||
static inline void *qed_chain_produce(struct qed_chain *p_chain)
|
||||
{
|
||||
void *ret = NULL;
|
||||
void *p_ret = NULL, *p_prod_idx, *p_prod_page_idx;
|
||||
|
||||
if ((p_chain->prod_idx & p_chain->elem_per_page_mask) ==
|
||||
p_chain->next_page_mask) {
|
||||
qed_chain_advance_page(p_chain, &p_chain->p_prod_elem,
|
||||
&p_chain->prod_idx,
|
||||
&p_chain->pbl.prod_page_idx);
|
||||
if (is_chain_u16(p_chain)) {
|
||||
if ((p_chain->u.chain16.prod_idx &
|
||||
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
|
||||
p_prod_idx = &p_chain->u.chain16.prod_idx;
|
||||
p_prod_page_idx = &p_chain->pbl.u.pbl16.prod_page_idx;
|
||||
qed_chain_advance_page(p_chain, &p_chain->p_prod_elem,
|
||||
p_prod_idx, p_prod_page_idx);
|
||||
}
|
||||
p_chain->u.chain16.prod_idx++;
|
||||
} else {
|
||||
if ((p_chain->u.chain32.prod_idx &
|
||||
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
|
||||
p_prod_idx = &p_chain->u.chain32.prod_idx;
|
||||
p_prod_page_idx = &p_chain->pbl.u.pbl32.prod_page_idx;
|
||||
qed_chain_advance_page(p_chain, &p_chain->p_prod_elem,
|
||||
p_prod_idx, p_prod_page_idx);
|
||||
}
|
||||
p_chain->u.chain32.prod_idx++;
|
||||
}
|
||||
|
||||
ret = p_chain->p_prod_elem;
|
||||
p_chain->prod_idx++;
|
||||
p_ret = p_chain->p_prod_elem;
|
||||
p_chain->p_prod_elem = (void *)(((u8 *)p_chain->p_prod_elem) +
|
||||
p_chain->elem_size);
|
||||
|
||||
return ret;
|
||||
return p_ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -282,9 +350,9 @@ static inline void *qed_chain_produce(struct qed_chain *p_chain)
|
|||
* @param p_chain
|
||||
* @param num
|
||||
*
|
||||
* @return u16, number of unusable BDs
|
||||
* @return number of unusable BDs
|
||||
*/
|
||||
static inline u16 qed_chain_get_capacity(struct qed_chain *p_chain)
|
||||
static inline u32 qed_chain_get_capacity(struct qed_chain *p_chain)
|
||||
{
|
||||
return p_chain->capacity;
|
||||
}
|
||||
|
@ -297,11 +365,13 @@ static inline u16 qed_chain_get_capacity(struct qed_chain *p_chain)
|
|||
*
|
||||
* @param p_chain
|
||||
*/
|
||||
static inline void
|
||||
qed_chain_recycle_consumed(struct qed_chain *p_chain)
|
||||
static inline void qed_chain_recycle_consumed(struct qed_chain *p_chain)
|
||||
{
|
||||
test_ans_skip(p_chain, prod_idx);
|
||||
p_chain->prod_idx++;
|
||||
test_and_skip(p_chain, prod_idx);
|
||||
if (is_chain_u16(p_chain))
|
||||
p_chain->u.chain16.prod_idx++;
|
||||
else
|
||||
p_chain->u.chain32.prod_idx++;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -316,21 +386,33 @@ qed_chain_recycle_consumed(struct qed_chain *p_chain)
|
|||
*/
|
||||
static inline void *qed_chain_consume(struct qed_chain *p_chain)
|
||||
{
|
||||
void *ret = NULL;
|
||||
void *p_ret = NULL, *p_cons_idx, *p_cons_page_idx;
|
||||
|
||||
if ((p_chain->cons_idx & p_chain->elem_per_page_mask) ==
|
||||
p_chain->next_page_mask) {
|
||||
if (is_chain_u16(p_chain)) {
|
||||
if ((p_chain->u.chain16.cons_idx &
|
||||
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
|
||||
p_cons_idx = &p_chain->u.chain16.cons_idx;
|
||||
p_cons_page_idx = &p_chain->pbl.u.pbl16.cons_page_idx;
|
||||
qed_chain_advance_page(p_chain, &p_chain->p_cons_elem,
|
||||
p_cons_idx, p_cons_page_idx);
|
||||
}
|
||||
p_chain->u.chain16.cons_idx++;
|
||||
} else {
|
||||
if ((p_chain->u.chain32.cons_idx &
|
||||
p_chain->elem_per_page_mask) == p_chain->next_page_mask) {
|
||||
p_cons_idx = &p_chain->u.chain32.cons_idx;
|
||||
p_cons_page_idx = &p_chain->pbl.u.pbl32.cons_page_idx;
|
||||
qed_chain_advance_page(p_chain, &p_chain->p_cons_elem,
|
||||
&p_chain->cons_idx,
|
||||
&p_chain->pbl.cons_page_idx);
|
||||
p_cons_idx, p_cons_page_idx);
|
||||
}
|
||||
p_chain->u.chain32.cons_idx++;
|
||||
}
|
||||
|
||||
ret = p_chain->p_cons_elem;
|
||||
p_chain->cons_idx++;
|
||||
p_ret = p_chain->p_cons_elem;
|
||||
p_chain->p_cons_elem = (void *)(((u8 *)p_chain->p_cons_elem) +
|
||||
p_chain->elem_size);
|
||||
|
||||
return ret;
|
||||
return p_ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -340,16 +422,33 @@ static inline void *qed_chain_consume(struct qed_chain *p_chain)
|
|||
*/
|
||||
static inline void qed_chain_reset(struct qed_chain *p_chain)
|
||||
{
|
||||
int i;
|
||||
u32 i;
|
||||
|
||||
p_chain->prod_idx = 0;
|
||||
p_chain->cons_idx = 0;
|
||||
p_chain->p_cons_elem = p_chain->p_virt_addr;
|
||||
p_chain->p_prod_elem = p_chain->p_virt_addr;
|
||||
if (is_chain_u16(p_chain)) {
|
||||
p_chain->u.chain16.prod_idx = 0;
|
||||
p_chain->u.chain16.cons_idx = 0;
|
||||
} else {
|
||||
p_chain->u.chain32.prod_idx = 0;
|
||||
p_chain->u.chain32.cons_idx = 0;
|
||||
}
|
||||
p_chain->p_cons_elem = p_chain->p_virt_addr;
|
||||
p_chain->p_prod_elem = p_chain->p_virt_addr;
|
||||
|
||||
if (p_chain->mode == QED_CHAIN_MODE_PBL) {
|
||||
p_chain->pbl.prod_page_idx = p_chain->page_cnt - 1;
|
||||
p_chain->pbl.cons_page_idx = p_chain->page_cnt - 1;
|
||||
/* Use (page_cnt - 1) as a reset value for the prod/cons page's
|
||||
* indices, to avoid unnecessary page advancing on the first
|
||||
* call to qed_chain_produce/consume. Instead, the indices
|
||||
* will be advanced to page_cnt and then will be wrapped to 0.
|
||||
*/
|
||||
u32 reset_val = p_chain->page_cnt - 1;
|
||||
|
||||
if (is_chain_u16(p_chain)) {
|
||||
p_chain->pbl.u.pbl16.prod_page_idx = (u16)reset_val;
|
||||
p_chain->pbl.u.pbl16.cons_page_idx = (u16)reset_val;
|
||||
} else {
|
||||
p_chain->pbl.u.pbl32.prod_page_idx = reset_val;
|
||||
p_chain->pbl.u.pbl32.cons_page_idx = reset_val;
|
||||
}
|
||||
}
|
||||
|
||||
switch (p_chain->intended_use) {
|
||||
|
@ -377,168 +476,184 @@ static inline void qed_chain_reset(struct qed_chain *p_chain)
|
|||
* @param intended_use
|
||||
* @param mode
|
||||
*/
|
||||
static inline void qed_chain_init(struct qed_chain *p_chain,
|
||||
void *p_virt_addr,
|
||||
dma_addr_t p_phys_addr,
|
||||
u16 page_cnt,
|
||||
u8 elem_size,
|
||||
enum qed_chain_use_mode intended_use,
|
||||
enum qed_chain_mode mode)
|
||||
static inline void qed_chain_init_params(struct qed_chain *p_chain,
|
||||
u32 page_cnt,
|
||||
u8 elem_size,
|
||||
enum qed_chain_use_mode intended_use,
|
||||
enum qed_chain_mode mode,
|
||||
enum qed_chain_cnt_type cnt_type)
|
||||
{
|
||||
/* chain fixed parameters */
|
||||
p_chain->p_virt_addr = p_virt_addr;
|
||||
p_chain->p_phys_addr = p_phys_addr;
|
||||
p_chain->p_virt_addr = NULL;
|
||||
p_chain->p_phys_addr = 0;
|
||||
p_chain->elem_size = elem_size;
|
||||
p_chain->page_cnt = page_cnt;
|
||||
p_chain->intended_use = intended_use;
|
||||
p_chain->mode = mode;
|
||||
p_chain->cnt_type = cnt_type;
|
||||
|
||||
p_chain->intended_use = intended_use;
|
||||
p_chain->elem_per_page = ELEMS_PER_PAGE(elem_size);
|
||||
p_chain->usable_per_page =
|
||||
USABLE_ELEMS_PER_PAGE(elem_size, mode);
|
||||
p_chain->capacity = p_chain->usable_per_page * page_cnt;
|
||||
p_chain->size = p_chain->elem_per_page * page_cnt;
|
||||
p_chain->usable_per_page = USABLE_ELEMS_PER_PAGE(elem_size, mode);
|
||||
p_chain->elem_per_page_mask = p_chain->elem_per_page - 1;
|
||||
|
||||
p_chain->elem_unusable = UNUSABLE_ELEMS_PER_PAGE(elem_size, mode);
|
||||
|
||||
p_chain->next_page_mask = (p_chain->usable_per_page &
|
||||
p_chain->elem_per_page_mask);
|
||||
|
||||
if (mode == QED_CHAIN_MODE_NEXT_PTR) {
|
||||
struct qed_chain_next *p_next;
|
||||
u16 i;
|
||||
p_chain->page_cnt = page_cnt;
|
||||
p_chain->capacity = p_chain->usable_per_page * page_cnt;
|
||||
p_chain->size = p_chain->elem_per_page * page_cnt;
|
||||
|
||||
for (i = 0; i < page_cnt - 1; i++) {
|
||||
/* Increment mem_phy to the next page. */
|
||||
p_phys_addr += QED_CHAIN_PAGE_SIZE;
|
||||
|
||||
/* Initialize the physical address of the next page. */
|
||||
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr +
|
||||
elem_size *
|
||||
p_chain->
|
||||
usable_per_page);
|
||||
|
||||
p_next->next_phys.lo = DMA_LO_LE(p_phys_addr);
|
||||
p_next->next_phys.hi = DMA_HI_LE(p_phys_addr);
|
||||
|
||||
/* Initialize the virtual address of the next page. */
|
||||
p_next->next_virt = (void *)((u8 *)p_virt_addr +
|
||||
QED_CHAIN_PAGE_SIZE);
|
||||
|
||||
/* Move to the next page. */
|
||||
p_virt_addr = p_next->next_virt;
|
||||
}
|
||||
|
||||
/* Last page's next should point to beginning of the chain */
|
||||
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr +
|
||||
elem_size *
|
||||
p_chain->usable_per_page);
|
||||
|
||||
p_next->next_phys.lo = DMA_LO_LE(p_chain->p_phys_addr);
|
||||
p_next->next_phys.hi = DMA_HI_LE(p_chain->p_phys_addr);
|
||||
p_next->next_virt = p_chain->p_virt_addr;
|
||||
}
|
||||
qed_chain_reset(p_chain);
|
||||
p_chain->pbl.p_phys_table = 0;
|
||||
p_chain->pbl.p_virt_table = NULL;
|
||||
p_chain->pbl.pp_virt_addr_tbl = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_pbl_init - Initalizes a basic pbl chain
|
||||
* struct
|
||||
* @brief qed_chain_init_mem -
|
||||
*
|
||||
* Initalizes a basic chain struct with its chain buffers
|
||||
*
|
||||
* @param p_chain
|
||||
* @param p_virt_addr virtual address of allocated buffer's beginning
|
||||
* @param p_phys_addr physical address of allocated buffer's beginning
|
||||
* @param page_cnt number of pages in the allocated buffer
|
||||
* @param elem_size size of each element in the chain
|
||||
* @param use_mode
|
||||
* @param p_phys_pbl pointer to a pre-allocated side table
|
||||
* which will hold physical page addresses.
|
||||
* @param p_virt_pbl pointer to a pre allocated side table
|
||||
* which will hold virtual page addresses.
|
||||
*
|
||||
*/
|
||||
static inline void
|
||||
qed_chain_pbl_init(struct qed_chain *p_chain,
|
||||
void *p_virt_addr,
|
||||
dma_addr_t p_phys_addr,
|
||||
u16 page_cnt,
|
||||
u8 elem_size,
|
||||
enum qed_chain_use_mode use_mode,
|
||||
dma_addr_t p_phys_pbl,
|
||||
dma_addr_t *p_virt_pbl)
|
||||
static inline void qed_chain_init_mem(struct qed_chain *p_chain,
|
||||
void *p_virt_addr, dma_addr_t p_phys_addr)
|
||||
{
|
||||
dma_addr_t *p_pbl_dma = p_virt_pbl;
|
||||
int i;
|
||||
|
||||
qed_chain_init(p_chain, p_virt_addr, p_phys_addr, page_cnt,
|
||||
elem_size, use_mode, QED_CHAIN_MODE_PBL);
|
||||
|
||||
p_chain->pbl.p_phys_table = p_phys_pbl;
|
||||
p_chain->pbl.p_virt_table = p_virt_pbl;
|
||||
|
||||
/* Fill the PBL with physical addresses*/
|
||||
for (i = 0; i < page_cnt; i++) {
|
||||
*p_pbl_dma = p_phys_addr;
|
||||
p_phys_addr += QED_CHAIN_PAGE_SIZE;
|
||||
p_pbl_dma++;
|
||||
}
|
||||
p_chain->p_virt_addr = p_virt_addr;
|
||||
p_chain->p_phys_addr = p_phys_addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_set_prod - sets the prod to the given
|
||||
* value
|
||||
* @brief qed_chain_init_pbl_mem -
|
||||
*
|
||||
* Initalizes a basic chain struct with its pbl buffers
|
||||
*
|
||||
* @param p_chain
|
||||
* @param p_virt_pbl pointer to a pre allocated side table which will hold
|
||||
* virtual page addresses.
|
||||
* @param p_phys_pbl pointer to a pre-allocated side table which will hold
|
||||
* physical page addresses.
|
||||
* @param pp_virt_addr_tbl
|
||||
* pointer to a pre-allocated side table which will hold
|
||||
* the virtual addresses of the chain pages.
|
||||
*
|
||||
*/
|
||||
static inline void qed_chain_init_pbl_mem(struct qed_chain *p_chain,
|
||||
void *p_virt_pbl,
|
||||
dma_addr_t p_phys_pbl,
|
||||
void **pp_virt_addr_tbl)
|
||||
{
|
||||
p_chain->pbl.p_phys_table = p_phys_pbl;
|
||||
p_chain->pbl.p_virt_table = p_virt_pbl;
|
||||
p_chain->pbl.pp_virt_addr_tbl = pp_virt_addr_tbl;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_init_next_ptr_elem -
|
||||
*
|
||||
* Initalizes a next pointer element
|
||||
*
|
||||
* @param p_chain
|
||||
* @param p_virt_curr virtual address of a chain page of which the next
|
||||
* pointer element is initialized
|
||||
* @param p_virt_next virtual address of the next chain page
|
||||
* @param p_phys_next physical address of the next chain page
|
||||
*
|
||||
*/
|
||||
static inline void
|
||||
qed_chain_init_next_ptr_elem(struct qed_chain *p_chain,
|
||||
void *p_virt_curr,
|
||||
void *p_virt_next, dma_addr_t p_phys_next)
|
||||
{
|
||||
struct qed_chain_next *p_next;
|
||||
u32 size;
|
||||
|
||||
size = p_chain->elem_size * p_chain->usable_per_page;
|
||||
p_next = (struct qed_chain_next *)((u8 *)p_virt_curr + size);
|
||||
|
||||
DMA_REGPAIR_LE(p_next->next_phys, p_phys_next);
|
||||
|
||||
p_next->next_virt = p_virt_next;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_get_last_elem -
|
||||
*
|
||||
* Returns a pointer to the last element of the chain
|
||||
*
|
||||
* @param p_chain
|
||||
*
|
||||
* @return void*
|
||||
*/
|
||||
static inline void *qed_chain_get_last_elem(struct qed_chain *p_chain)
|
||||
{
|
||||
struct qed_chain_next *p_next = NULL;
|
||||
void *p_virt_addr = NULL;
|
||||
u32 size, last_page_idx;
|
||||
|
||||
if (!p_chain->p_virt_addr)
|
||||
goto out;
|
||||
|
||||
switch (p_chain->mode) {
|
||||
case QED_CHAIN_MODE_NEXT_PTR:
|
||||
size = p_chain->elem_size * p_chain->usable_per_page;
|
||||
p_virt_addr = p_chain->p_virt_addr;
|
||||
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr + size);
|
||||
while (p_next->next_virt != p_chain->p_virt_addr) {
|
||||
p_virt_addr = p_next->next_virt;
|
||||
p_next = (struct qed_chain_next *)((u8 *)p_virt_addr +
|
||||
size);
|
||||
}
|
||||
break;
|
||||
case QED_CHAIN_MODE_SINGLE:
|
||||
p_virt_addr = p_chain->p_virt_addr;
|
||||
break;
|
||||
case QED_CHAIN_MODE_PBL:
|
||||
last_page_idx = p_chain->page_cnt - 1;
|
||||
p_virt_addr = p_chain->pbl.pp_virt_addr_tbl[last_page_idx];
|
||||
break;
|
||||
}
|
||||
/* p_virt_addr points at this stage to the last page of the chain */
|
||||
size = p_chain->elem_size * (p_chain->usable_per_page - 1);
|
||||
p_virt_addr = (u8 *)p_virt_addr + size;
|
||||
out:
|
||||
return p_virt_addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_set_prod - sets the prod to the given value
|
||||
*
|
||||
* @param prod_idx
|
||||
* @param p_prod_elem
|
||||
*/
|
||||
static inline void qed_chain_set_prod(struct qed_chain *p_chain,
|
||||
u16 prod_idx,
|
||||
void *p_prod_elem)
|
||||
u32 prod_idx, void *p_prod_elem)
|
||||
{
|
||||
p_chain->prod_idx = prod_idx;
|
||||
p_chain->p_prod_elem = p_prod_elem;
|
||||
if (is_chain_u16(p_chain))
|
||||
p_chain->u.chain16.prod_idx = (u16) prod_idx;
|
||||
else
|
||||
p_chain->u.chain32.prod_idx = prod_idx;
|
||||
p_chain->p_prod_elem = p_prod_elem;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_get_elem -
|
||||
*
|
||||
* get a pointer to an element represented by absolute idx
|
||||
* @brief qed_chain_pbl_zero_mem - set chain memory to 0
|
||||
*
|
||||
* @param p_chain
|
||||
* @assumption p_chain->size is a power of 2
|
||||
*
|
||||
* @return void*, a pointer to next element
|
||||
*/
|
||||
static inline void *qed_chain_sge_get_elem(struct qed_chain *p_chain,
|
||||
u16 idx)
|
||||
static inline void qed_chain_pbl_zero_mem(struct qed_chain *p_chain)
|
||||
{
|
||||
void *ret = NULL;
|
||||
u32 i, page_cnt;
|
||||
|
||||
if (idx >= p_chain->size)
|
||||
return NULL;
|
||||
if (p_chain->mode != QED_CHAIN_MODE_PBL)
|
||||
return;
|
||||
|
||||
ret = (u8 *)p_chain->p_virt_addr + p_chain->elem_size * idx;
|
||||
page_cnt = qed_chain_get_page_cnt(p_chain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief qed_chain_sge_inc_cons_prod
|
||||
*
|
||||
* for sge chains, producer isn't increased serially, the ring
|
||||
* is expected to be full at all times. Once elements are
|
||||
* consumed, they are immediately produced.
|
||||
*
|
||||
* @param p_chain
|
||||
* @param cnt
|
||||
*
|
||||
* @return inline void
|
||||
*/
|
||||
static inline void
|
||||
qed_chain_sge_inc_cons_prod(struct qed_chain *p_chain,
|
||||
u16 cnt)
|
||||
{
|
||||
p_chain->prod_idx += cnt;
|
||||
p_chain->cons_idx += cnt;
|
||||
for (i = 0; i < page_cnt; i++)
|
||||
memset(p_chain->pbl.pp_virt_addr_tbl[i], 0,
|
||||
QED_CHAIN_PAGE_SIZE);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -58,8 +58,70 @@ struct qed_eth_pf_params {
|
|||
u16 num_cons;
|
||||
};
|
||||
|
||||
/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
|
||||
struct qed_iscsi_pf_params {
|
||||
u64 glbl_q_params_addr;
|
||||
u64 bdq_pbl_base_addr[2];
|
||||
u32 max_cwnd;
|
||||
u16 cq_num_entries;
|
||||
u16 cmdq_num_entries;
|
||||
u16 dup_ack_threshold;
|
||||
u16 tx_sws_timer;
|
||||
u16 min_rto;
|
||||
u16 min_rto_rt;
|
||||
u16 max_rto;
|
||||
|
||||
/* The following parameters are used during HW-init
|
||||
* and these parameters need to be passed as arguments
|
||||
* to update_pf_params routine invoked before slowpath start
|
||||
*/
|
||||
u16 num_cons;
|
||||
u16 num_tasks;
|
||||
|
||||
/* The following parameters are used during protocol-init */
|
||||
u16 half_way_close_timeout;
|
||||
u16 bdq_xoff_threshold[2];
|
||||
u16 bdq_xon_threshold[2];
|
||||
u16 cmdq_xoff_threshold;
|
||||
u16 cmdq_xon_threshold;
|
||||
u16 rq_buffer_size;
|
||||
|
||||
u8 num_sq_pages_in_ring;
|
||||
u8 num_r2tq_pages_in_ring;
|
||||
u8 num_uhq_pages_in_ring;
|
||||
u8 num_queues;
|
||||
u8 log_page_size;
|
||||
u8 rqe_log_size;
|
||||
u8 max_fin_rt;
|
||||
u8 gl_rq_pi;
|
||||
u8 gl_cmd_pi;
|
||||
u8 debug_mode;
|
||||
u8 ll2_ooo_queue_id;
|
||||
u8 ooo_enable;
|
||||
|
||||
u8 is_target;
|
||||
u8 bdq_pbl_num_entries[2];
|
||||
};
|
||||
|
||||
struct qed_rdma_pf_params {
|
||||
/* Supplied to QED during resource allocation (may affect the ILT and
|
||||
* the doorbell BAR).
|
||||
*/
|
||||
u32 min_dpis; /* number of requested DPIs */
|
||||
u32 num_mrs; /* number of requested memory regions */
|
||||
u32 num_qps; /* number of requested Queue Pairs */
|
||||
u32 num_srqs; /* number of requested SRQ */
|
||||
u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
|
||||
u8 gl_pi; /* protocol index */
|
||||
|
||||
/* Will allocate rate limiters to be used with QPs */
|
||||
u8 enable_dcqcn;
|
||||
};
|
||||
|
||||
struct qed_pf_params {
|
||||
struct qed_eth_pf_params eth_pf_params;
|
||||
struct qed_iscsi_pf_params iscsi_pf_params;
|
||||
struct qed_rdma_pf_params rdma_pf_params;
|
||||
};
|
||||
|
||||
enum qed_int_mode {
|
||||
|
@ -100,6 +162,8 @@ struct qed_dev_info {
|
|||
/* MFW version */
|
||||
u32 mfw_rev;
|
||||
|
||||
bool rdma_supported;
|
||||
|
||||
u32 flash_size;
|
||||
u8 mf_mode;
|
||||
bool tx_switching;
|
||||
|
@ -111,6 +175,7 @@ enum qed_sb_type {
|
|||
|
||||
enum qed_protocol {
|
||||
QED_PROTOCOL_ETH,
|
||||
QED_PROTOCOL_ISCSI,
|
||||
};
|
||||
|
||||
struct qed_link_params {
|
||||
|
@ -325,7 +390,8 @@ struct qed_common_ops {
|
|||
int (*chain_alloc)(struct qed_dev *cdev,
|
||||
enum qed_chain_use_mode intended_use,
|
||||
enum qed_chain_mode mode,
|
||||
u16 num_elems,
|
||||
enum qed_chain_cnt_type cnt_type,
|
||||
u32 num_elems,
|
||||
size_t elem_size,
|
||||
struct qed_chain *p_chain);
|
||||
|
||||
|
|
44
include/linux/qed/rdma_common.h
Normal file
44
include/linux/qed/rdma_common.h
Normal file
|
@ -0,0 +1,44 @@
|
|||
/* QLogic qed NIC Driver
|
||||
* Copyright (c) 2015 QLogic Corporation
|
||||
*
|
||||
* This software is available under the terms of the GNU General Public License
|
||||
* (GPL) Version 2, available from the file COPYING in the main directory of
|
||||
* this source tree.
|
||||
*/
|
||||
|
||||
#ifndef __RDMA_COMMON__
|
||||
#define __RDMA_COMMON__
|
||||
/************************/
|
||||
/* RDMA FW CONSTANTS */
|
||||
/************************/
|
||||
|
||||
#define RDMA_RESERVED_LKEY (0)
|
||||
#define RDMA_RING_PAGE_SIZE (0x1000)
|
||||
|
||||
#define RDMA_MAX_SGE_PER_SQ_WQE (4)
|
||||
#define RDMA_MAX_SGE_PER_RQ_WQE (4)
|
||||
|
||||
#define RDMA_MAX_DATA_SIZE_IN_WQE (0x7FFFFFFF)
|
||||
|
||||
#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
|
||||
#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
|
||||
|
||||
#define RDMA_MAX_CQS (64 * 1024)
|
||||
#define RDMA_MAX_TIDS (128 * 1024 - 1)
|
||||
#define RDMA_MAX_PDS (64 * 1024)
|
||||
|
||||
#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
|
||||
|
||||
#define RDMA_TASK_TYPE (PROTOCOLID_ROCE)
|
||||
|
||||
struct rdma_srq_id {
|
||||
__le16 srq_idx;
|
||||
__le16 opaque_fid;
|
||||
};
|
||||
|
||||
struct rdma_srq_producers {
|
||||
__le32 sge_prod;
|
||||
__le32 wqe_prod;
|
||||
};
|
||||
|
||||
#endif /* __RDMA_COMMON__ */
|
17
include/linux/qed/roce_common.h
Normal file
17
include/linux/qed/roce_common.h
Normal file
|
@ -0,0 +1,17 @@
|
|||
/* QLogic qed NIC Driver
|
||||
* Copyright (c) 2015 QLogic Corporation
|
||||
*
|
||||
* This software is available under the terms of the GNU General Public License
|
||||
* (GPL) Version 2, available from the file COPYING in the main directory of
|
||||
* this source tree.
|
||||
*/
|
||||
|
||||
#ifndef __ROCE_COMMON__
|
||||
#define __ROCE_COMMON__
|
||||
|
||||
#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
|
||||
#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
|
||||
|
||||
#define ROCE_MAX_QPS (32 * 1024)
|
||||
|
||||
#endif /* __ROCE_COMMON__ */
|
91
include/linux/qed/storage_common.h
Normal file
91
include/linux/qed/storage_common.h
Normal file
|
@ -0,0 +1,91 @@
|
|||
/* QLogic qed NIC Driver
|
||||
* Copyright (c) 2015 QLogic Corporation
|
||||
*
|
||||
* This software is available under the terms of the GNU General Public License
|
||||
* (GPL) Version 2, available from the file COPYING in the main directory of
|
||||
* this source tree.
|
||||
*/
|
||||
|
||||
#ifndef __STORAGE_COMMON__
|
||||
#define __STORAGE_COMMON__
|
||||
|
||||
#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2)
|
||||
#define BDQ_NUM_RESOURCES (4)
|
||||
|
||||
#define BDQ_ID_RQ (0)
|
||||
#define BDQ_ID_IMM_DATA (1)
|
||||
#define BDQ_NUM_IDS (2)
|
||||
|
||||
#define BDQ_MAX_EXTERNAL_RING_SIZE (1 << 15)
|
||||
|
||||
struct scsi_bd {
|
||||
struct regpair address;
|
||||
struct regpair opaque;
|
||||
};
|
||||
|
||||
struct scsi_bdq_ram_drv_data {
|
||||
__le16 external_producer;
|
||||
__le16 reserved0[3];
|
||||
};
|
||||
|
||||
struct scsi_drv_cmdq {
|
||||
__le16 cmdq_cons;
|
||||
__le16 reserved0;
|
||||
__le32 reserved1;
|
||||
};
|
||||
|
||||
struct scsi_init_func_params {
|
||||
__le16 num_tasks;
|
||||
u8 log_page_size;
|
||||
u8 debug_mode;
|
||||
u8 reserved2[12];
|
||||
};
|
||||
|
||||
struct scsi_init_func_queues {
|
||||
struct regpair glbl_q_params_addr;
|
||||
__le16 rq_buffer_size;
|
||||
__le16 cq_num_entries;
|
||||
__le16 cmdq_num_entries;
|
||||
u8 bdq_resource_id;
|
||||
u8 q_validity;
|
||||
#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
|
||||
#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0
|
||||
#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
|
||||
#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1
|
||||
#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
|
||||
#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2
|
||||
#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_MASK 0x1F
|
||||
#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_SHIFT 3
|
||||
u8 num_queues;
|
||||
u8 queue_relative_offset;
|
||||
u8 cq_sb_pi;
|
||||
u8 cmdq_sb_pi;
|
||||
__le16 cq_cmdq_sb_num_arr[NUM_OF_CMDQS_CQS];
|
||||
__le16 reserved0;
|
||||
u8 bdq_pbl_num_entries[BDQ_NUM_IDS];
|
||||
struct regpair bdq_pbl_base_address[BDQ_NUM_IDS];
|
||||
__le16 bdq_xoff_threshold[BDQ_NUM_IDS];
|
||||
__le16 bdq_xon_threshold[BDQ_NUM_IDS];
|
||||
__le16 cmdq_xoff_threshold;
|
||||
__le16 cmdq_xon_threshold;
|
||||
__le32 reserved1;
|
||||
};
|
||||
|
||||
struct scsi_ram_per_bdq_resource_drv_data {
|
||||
struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS];
|
||||
};
|
||||
|
||||
struct scsi_sge {
|
||||
struct regpair sge_addr;
|
||||
__le16 sge_len;
|
||||
__le16 reserved0;
|
||||
__le32 reserved1;
|
||||
};
|
||||
|
||||
struct scsi_terminate_extra_params {
|
||||
__le16 unsolicited_cq_count;
|
||||
__le16 cmdq_count;
|
||||
u8 reserved[4];
|
||||
};
|
||||
|
||||
#endif /* __STORAGE_COMMON__ */
|
226
include/linux/qed/tcp_common.h
Normal file
226
include/linux/qed/tcp_common.h
Normal file
|
@ -0,0 +1,226 @@
|
|||
/* QLogic qed NIC Driver
|
||||
* Copyright (c) 2015 QLogic Corporation
|
||||
*
|
||||
* This software is available under the terms of the GNU General Public License
|
||||
* (GPL) Version 2, available from the file COPYING in the main directory of
|
||||
* this source tree.
|
||||
*/
|
||||
|
||||
#ifndef __TCP_COMMON__
|
||||
#define __TCP_COMMON__
|
||||
|
||||
#define TCP_INVALID_TIMEOUT_VAL -1
|
||||
|
||||
enum tcp_connect_mode {
|
||||
TCP_CONNECT_ACTIVE,
|
||||
TCP_CONNECT_PASSIVE,
|
||||
MAX_TCP_CONNECT_MODE
|
||||
};
|
||||
|
||||
struct tcp_init_params {
|
||||
__le32 max_cwnd;
|
||||
__le16 dup_ack_threshold;
|
||||
__le16 tx_sws_timer;
|
||||
__le16 min_rto;
|
||||
__le16 min_rto_rt;
|
||||
__le16 max_rto;
|
||||
u8 maxfinrt;
|
||||
u8 reserved[1];
|
||||
};
|
||||
|
||||
enum tcp_ip_version {
|
||||
TCP_IPV4,
|
||||
TCP_IPV6,
|
||||
MAX_TCP_IP_VERSION
|
||||
};
|
||||
|
||||
struct tcp_offload_params {
|
||||
__le16 local_mac_addr_lo;
|
||||
__le16 local_mac_addr_mid;
|
||||
__le16 local_mac_addr_hi;
|
||||
__le16 remote_mac_addr_lo;
|
||||
__le16 remote_mac_addr_mid;
|
||||
__le16 remote_mac_addr_hi;
|
||||
__le16 vlan_id;
|
||||
u8 flags;
|
||||
#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0
|
||||
#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1
|
||||
#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2
|
||||
#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 3
|
||||
#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 4
|
||||
#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 5
|
||||
#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 6
|
||||
#define TCP_OFFLOAD_PARAMS_RESERVED0_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_RESERVED0_SHIFT 7
|
||||
u8 ip_version;
|
||||
__le32 remote_ip[4];
|
||||
__le32 local_ip[4];
|
||||
__le32 flow_label;
|
||||
u8 ttl;
|
||||
u8 tos_or_tc;
|
||||
__le16 remote_port;
|
||||
__le16 local_port;
|
||||
__le16 mss;
|
||||
u8 rcv_wnd_scale;
|
||||
u8 connect_mode;
|
||||
__le16 srtt;
|
||||
__le32 cwnd;
|
||||
__le32 ss_thresh;
|
||||
__le16 reserved1;
|
||||
u8 ka_max_probe_cnt;
|
||||
u8 dup_ack_theshold;
|
||||
__le32 rcv_next;
|
||||
__le32 snd_una;
|
||||
__le32 snd_next;
|
||||
__le32 snd_max;
|
||||
__le32 snd_wnd;
|
||||
__le32 rcv_wnd;
|
||||
__le32 snd_wl1;
|
||||
__le32 ts_time;
|
||||
__le32 ts_recent;
|
||||
__le32 ts_recent_age;
|
||||
__le32 total_rt;
|
||||
__le32 ka_timeout_delta;
|
||||
__le32 rt_timeout_delta;
|
||||
u8 dup_ack_cnt;
|
||||
u8 snd_wnd_probe_cnt;
|
||||
u8 ka_probe_cnt;
|
||||
u8 rt_cnt;
|
||||
__le16 rtt_var;
|
||||
__le16 reserved2;
|
||||
__le32 ka_timeout;
|
||||
__le32 ka_interval;
|
||||
__le32 max_rt_time;
|
||||
__le32 initial_rcv_wnd;
|
||||
u8 snd_wnd_scale;
|
||||
u8 ack_frequency;
|
||||
__le16 da_timeout_value;
|
||||
__le32 ts_ticks_per_second;
|
||||
};
|
||||
|
||||
struct tcp_offload_params_opt2 {
|
||||
__le16 local_mac_addr_lo;
|
||||
__le16 local_mac_addr_mid;
|
||||
__le16 local_mac_addr_hi;
|
||||
__le16 remote_mac_addr_lo;
|
||||
__le16 remote_mac_addr_mid;
|
||||
__le16 remote_mac_addr_hi;
|
||||
__le16 vlan_id;
|
||||
u8 flags;
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0x1F
|
||||
#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 3
|
||||
u8 ip_version;
|
||||
__le32 remote_ip[4];
|
||||
__le32 local_ip[4];
|
||||
__le32 flow_label;
|
||||
u8 ttl;
|
||||
u8 tos_or_tc;
|
||||
__le16 remote_port;
|
||||
__le16 local_port;
|
||||
__le16 mss;
|
||||
u8 rcv_wnd_scale;
|
||||
u8 connect_mode;
|
||||
__le16 syn_ip_payload_length;
|
||||
__le32 syn_phy_addr_lo;
|
||||
__le32 syn_phy_addr_hi;
|
||||
__le32 reserved1[22];
|
||||
};
|
||||
|
||||
enum tcp_seg_placement_event {
|
||||
TCP_EVENT_ADD_PEN,
|
||||
TCP_EVENT_ADD_NEW_ISLE,
|
||||
TCP_EVENT_ADD_ISLE_RIGHT,
|
||||
TCP_EVENT_ADD_ISLE_LEFT,
|
||||
TCP_EVENT_JOIN,
|
||||
TCP_EVENT_NOP,
|
||||
MAX_TCP_SEG_PLACEMENT_EVENT
|
||||
};
|
||||
|
||||
struct tcp_update_params {
|
||||
__le16 flags;
|
||||
#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0
|
||||
#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1
|
||||
#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2
|
||||
#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3
|
||||
#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4
|
||||
#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5
|
||||
#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6
|
||||
#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7
|
||||
#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8
|
||||
#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9
|
||||
#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10
|
||||
#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11
|
||||
#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12
|
||||
#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13
|
||||
#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14
|
||||
#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1
|
||||
#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15
|
||||
__le16 remote_mac_addr_lo;
|
||||
__le16 remote_mac_addr_mid;
|
||||
__le16 remote_mac_addr_hi;
|
||||
__le16 mss;
|
||||
u8 ttl;
|
||||
u8 tos_or_tc;
|
||||
__le32 ka_timeout;
|
||||
__le32 ka_interval;
|
||||
__le32 max_rt_time;
|
||||
__le32 flow_label;
|
||||
__le32 initial_rcv_wnd;
|
||||
u8 ka_max_probe_cnt;
|
||||
u8 reserved1[7];
|
||||
};
|
||||
|
||||
struct tcp_upload_params {
|
||||
__le32 rcv_next;
|
||||
__le32 snd_una;
|
||||
__le32 snd_next;
|
||||
__le32 snd_max;
|
||||
__le32 snd_wnd;
|
||||
__le32 rcv_wnd;
|
||||
__le32 snd_wl1;
|
||||
__le32 cwnd;
|
||||
__le32 ss_thresh;
|
||||
__le16 srtt;
|
||||
__le16 rtt_var;
|
||||
__le32 ts_time;
|
||||
__le32 ts_recent;
|
||||
__le32 ts_recent_age;
|
||||
__le32 total_rt;
|
||||
__le32 ka_timeout_delta;
|
||||
__le32 rt_timeout_delta;
|
||||
u8 dup_ack_cnt;
|
||||
u8 snd_wnd_probe_cnt;
|
||||
u8 ka_probe_cnt;
|
||||
u8 rt_cnt;
|
||||
__le32 reserved;
|
||||
};
|
||||
|
||||
#endif /* __TCP_COMMON__ */
|
Loading…
Reference in a new issue