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MLK-23728: Fix ov2775 dtb for imx8mp 

Move mipi_csi clock changes from imx8mp.dtsi into 0v2775 dtb,
to avoid failures for ov5460.
Tested with VSI ISP demo 28/02/20 release.
Not tested with camera on CSI2.

Fixes: 636de0a39e ("Add ov2775 dtb for imx8mp")
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Acked-by: G.n. Zhou <guoniu.zhou@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Mirela Rabulea 2020-04-13 11:52:35 +03:00
parent f6298e826b
commit 041b13b1f6
2 changed files with 22 additions and 8 deletions
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14
arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts
View File

@ -82,3 +82,17 @@
&isi_1 {
status = "disabled";
};
&mipi_csi_0 {
clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "mipi_clk", "axi_root", "apb_root";
};
&mipi_csi_1 {
clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "mipi_clk", "axi_root", "apb_root";
};

16
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -1791,9 +1791,9 @@
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "mipi_clk", "axi_root", "apb_root";
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "disp_axi", "disp_apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
@ -1810,14 +1810,14 @@
compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
reg = <0x32e50000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "mipi_clk", "axi_root", "apb_root";
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "disp_axi", "disp_apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
assigned-clock-rates = <266000000>;
bus-width = <4>;
csi-gpr = <&mediamix_gasket1>;
csi-gpr2 = <&mediamix_gpr>;