drm/nvc0/pm: initial engine reclocking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>hifive-unleashed-5.1
Ben Skeggs
parent
52c4d76743
commit
045da4e555
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@ -72,6 +72,8 @@ int nva3_pm_clocks_set(struct drm_device *, void *);
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/* nvc0_pm.c */
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int nvc0_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nvc0_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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int nvc0_pm_clocks_set(struct drm_device *, void *);
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/* nouveau_temp.c */
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void nouveau_temp_init(struct drm_device *dev);
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@ -417,6 +417,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->vram.flags_valid = nvc0_vram_flags_valid;
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engine->pm.temp_get = nv84_temp_get;
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engine->pm.clocks_get = nvc0_pm_clocks_get;
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engine->pm.clocks_pre = nvc0_pm_clocks_pre;
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engine->pm.clocks_set = nvc0_pm_clocks_set;
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engine->pm.voltage_get = nouveau_voltage_gpio_get;
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engine->pm.voltage_set = nouveau_voltage_gpio_set;
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engine->pm.pwm_get = nv50_pm_pwm_get;
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@ -468,6 +470,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->vram.flags_valid = nvc0_vram_flags_valid;
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engine->pm.temp_get = nv84_temp_get;
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engine->pm.clocks_get = nvc0_pm_clocks_get;
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engine->pm.clocks_pre = nvc0_pm_clocks_pre;
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engine->pm.clocks_set = nvc0_pm_clocks_set;
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engine->pm.voltage_get = nouveau_voltage_gpio_get;
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engine->pm.voltage_set = nouveau_voltage_gpio_set;
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break;
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@ -153,3 +153,240 @@ nvc0_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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perflvl->vdec = read_clk(dev, 0x0e);
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return 0;
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}
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struct nvc0_pm_clock {
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u32 freq;
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u32 ssel;
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u32 mdiv;
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u32 dsrc;
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u32 ddiv;
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u32 coef;
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};
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struct nvc0_pm_state {
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struct nvc0_pm_clock eng[16];
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};
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static u32
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calc_div(struct drm_device *dev, int clk, u32 ref, u32 freq, u32 *ddiv)
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{
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u32 div = min((ref * 2) / freq, (u32)65);
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if (div < 2)
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div = 2;
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*ddiv = div - 2;
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return (ref * 2) / div;
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}
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static u32
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calc_src(struct drm_device *dev, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
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{
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u32 sclk;
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/* use one of the fixed frequencies if possible */
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*ddiv = 0x00000000;
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switch (freq) {
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case 27000:
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case 108000:
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*dsrc = 0x00000000;
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if (freq == 108000)
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*dsrc |= 0x00030000;
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return freq;
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case 100000:
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*dsrc = 0x00000002;
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return freq;
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default:
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*dsrc = 0x00000003;
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break;
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}
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/* otherwise, calculate the closest divider */
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sclk = read_vco(dev, clk);
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if (clk < 7)
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sclk = calc_div(dev, clk, sclk, freq, ddiv);
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return sclk;
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}
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static u32
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calc_pll(struct drm_device *dev, int clk, u32 freq, u32 *coef)
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{
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struct pll_lims limits;
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int N, M, P, ret;
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ret = get_pll_limits(dev, 0x137000 + (clk * 0x20), &limits);
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if (ret)
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return 0;
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limits.refclk = read_div(dev, clk, 0x137120, 0x137140);
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if (!limits.refclk)
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return 0;
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ret = nva3_calc_pll(dev, &limits, freq, &N, NULL, &M, &P);
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if (ret <= 0)
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return 0;
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*coef = (P << 16) | (N << 8) | M;
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return ret;
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}
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/* A (likely rather simplified and incomplete) view of the clock tree
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*
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* Key:
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*
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* S: source select
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* D: divider
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* P: pll
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* F: switch
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*
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* Engine clocks:
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*
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* 137250(D) ---- 137100(F0) ---- 137160(S)/1371d0(D) ------------------- ref
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* (F1) ---- 1370X0(P) ---- 137120(S)/137140(D) ---- ref
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*
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* Not all registers exist for all clocks. For example: clocks >= 8 don't
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* have their own PLL (all tied to clock 7's PLL when in PLL mode), nor do
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* they have the divider at 1371d0, though the source selection at 137160
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* still exists. You must use the divider at 137250 for these instead.
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*
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* Memory clock:
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*
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* TBD, read_mem() above is likely very wrong...
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*
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*/
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static int
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calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
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{
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u32 src0, div0, div1D, div1P = 0;
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u32 clk0, clk1 = 0;
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/* invalid clock domain */
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if (!freq)
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return 0;
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/* first possible path, using only dividers */
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clk0 = calc_src(dev, clk, freq, &src0, &div0);
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clk0 = calc_div(dev, clk, clk0, freq, &div1D);
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/* see if we can get any closer using PLLs */
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if (clk0 != freq) {
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if (clk < 7)
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clk1 = calc_pll(dev, clk, freq, &info->coef);
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else
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clk1 = read_pll(dev, 0x1370e0);
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clk1 = calc_div(dev, clk, clk1, freq, &div1P);
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}
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/* select the method which gets closest to target freq */
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if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
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info->dsrc = src0;
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if (div0) {
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info->ddiv |= 0x80000000;
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info->ddiv |= div0 << 8;
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info->ddiv |= div0;
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}
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if (div1D) {
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info->mdiv |= 0x80000000;
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info->mdiv |= div1D;
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}
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info->ssel = 0;
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info->freq = clk0;
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} else {
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if (div1P) {
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info->mdiv |= 0x80000000;
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info->mdiv |= div1P << 8;
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}
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info->ssel = (1 << clk);
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info->freq = clk1;
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}
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return 0;
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}
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void *
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nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvc0_pm_state *info;
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int ret;
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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/* NFI why this is still in the performance table, the ROPCs appear
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* to get their clock from clock 2 ("hub07", actually hub05 on this
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* chip, but, anyway...) as well. nvatiming confirms hub05 and ROP
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* are always the same freq with the binary driver even when the
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* performance table says they should differ.
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*/
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if (dev_priv->chipset == 0xd9)
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perflvl->rop = 0;
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if ((ret = calc_clk(dev, 0x00, &info->eng[0x00], perflvl->shader)) ||
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(ret = calc_clk(dev, 0x01, &info->eng[0x01], perflvl->rop)) ||
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(ret = calc_clk(dev, 0x02, &info->eng[0x02], perflvl->hub07)) ||
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(ret = calc_clk(dev, 0x07, &info->eng[0x07], perflvl->hub06)) ||
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(ret = calc_clk(dev, 0x08, &info->eng[0x08], perflvl->hub01)) ||
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(ret = calc_clk(dev, 0x09, &info->eng[0x09], perflvl->copy)) ||
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(ret = calc_clk(dev, 0x0c, &info->eng[0x0c], perflvl->daemon)) ||
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(ret = calc_clk(dev, 0x0e, &info->eng[0x0e], perflvl->vdec))) {
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kfree(info);
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return ERR_PTR(ret);
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}
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return info;
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}
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static void
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prog_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info)
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{
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/* program dividers at 137160/1371d0 first */
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if (clk < 7 && !info->ssel) {
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nv_mask(dev, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
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nv_wr32(dev, 0x137160 + (clk * 0x04), info->dsrc);
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}
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/* switch clock to non-pll mode */
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nv_mask(dev, 0x137100, (1 << clk), 0x00000000);
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nv_wait(dev, 0x137100, (1 << clk), 0x00000000);
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/* reprogram pll */
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if (clk < 7) {
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/* make sure it's disabled first... */
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u32 base = 0x137000 + (clk * 0x20);
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u32 ctrl = nv_rd32(dev, base + 0x00);
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if (ctrl & 0x00000001) {
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nv_mask(dev, base + 0x00, 0x00000004, 0x00000000);
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nv_mask(dev, base + 0x00, 0x00000001, 0x00000000);
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}
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/* program it to new values, if necessary */
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if (info->ssel) {
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nv_wr32(dev, base + 0x04, info->coef);
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nv_mask(dev, base + 0x00, 0x00000001, 0x00000001);
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nv_wait(dev, base + 0x00, 0x00020000, 0x00020000);
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nv_mask(dev, base + 0x00, 0x00020004, 0x00000004);
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}
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}
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/* select pll/non-pll mode, and program final clock divider */
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nv_mask(dev, 0x137100, (1 << clk), info->ssel);
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nv_wait(dev, 0x137100, (1 << clk), info->ssel);
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nv_mask(dev, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
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}
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int
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nvc0_pm_clocks_set(struct drm_device *dev, void *data)
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{
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struct nvc0_pm_state *info = data;
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int i;
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for (i = 0; i < 16; i++) {
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if (!info->eng[i].freq)
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continue;
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prog_clk(dev, i, &info->eng[i]);
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}
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kfree(info);
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return 0;
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}
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