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Merge branch 'cxgb4-Reference-count-MPS-TCAM-entries-within-a-PF' 

Raju Rangoju says:

====================
cxgb4: Reference count MPS TCAM entries within a PF

Firmware reference counts the MPS TCAM entries by PF and VF,
but it does not do it for usage within a PF or VF. This patch
adds the support to track MPS TCAM entries within a PF.

v2->v3:
 Fixed the compiler errors due to incorrect patch
 Also, removed the new blank line at EOF
v1->v2:
 Use refcount_t type instead of atomic_t for mps reference count
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
alistair/sunxi64-5.4-dsi
David S. Miller 2019-06-24 14:54:06 -07:00
parent 0fec7e72ae f9f329ad87
commit 045df37e74
5 changed files with 312 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/chelsio/cxgb4/Makefile
View File

@ -7,7 +7,7 @@ obj-$(CONFIG_CHELSIO_T4) += cxgb4.o
cxgb4-objs := cxgb4_main.o l2t.o smt.o t4_hw.o sge.o clip_tbl.o cxgb4_ethtool.o \
cxgb4_uld.o srq.o sched.o cxgb4_filter.o cxgb4_tc_u32.o \
cxgb4_ptp.o cxgb4_tc_flower.o cxgb4_cudbg.o \
cxgb4_ptp.o cxgb4_tc_flower.o cxgb4_cudbg.o cxgb4_mps.o \
cudbg_common.o cudbg_lib.o cudbg_zlib.o
cxgb4-$(CONFIG_CHELSIO_T4_DCB) += cxgb4_dcb.o
cxgb4-$(CONFIG_CHELSIO_T4_FCOE) += cxgb4_fcoe.o

53
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
View File

@ -905,10 +905,6 @@ struct mbox_list {
struct list_head list;
};
struct mps_encap_entry {
atomic_t refcnt;
};
#if IS_ENABLED(CONFIG_THERMAL)
struct ch_thermal {
struct thermal_zone_device *tzdev;
@ -917,6 +913,14 @@ struct ch_thermal {
};
#endif
struct mps_entries_ref {
struct list_head list;
u8 addr[ETH_ALEN];
u8 mask[ETH_ALEN];
u16 idx;
refcount_t refcnt;
};
struct adapter {
void __iomem *regs;
void __iomem *bar2;
@ -969,7 +973,6 @@ struct adapter {
unsigned int rawf_start;
unsigned int rawf_cnt;
struct smt_data *smt;
struct mps_encap_entry *mps_encap;
struct cxgb4_uld_info *uld;
void *uld_handle[CXGB4_ULD_MAX];
unsigned int num_uld;
@ -977,6 +980,8 @@ struct adapter {
struct list_head list_node;
struct list_head rcu_node;
struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
struct list_head mps_ref;
spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */
void *iscsi_ppm;
@ -1906,4 +1911,42 @@ int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
cpumask_var_t *aff_mask, int idx);
void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
int *tcam_idx, const u8 *addr,
bool persistent, u8 *smt_idx);
int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
bool free, unsigned int naddr,
const u8 **addr, u16 *idx,
u64 *hash, bool sleep_ok);
int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
unsigned int naddr, const u8 **addr, bool sleep_ok);
int cxgb4_init_mps_ref_entries(struct adapter *adap);
void cxgb4_free_mps_ref_entries(struct adapter *adap);
int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
const u8 *addr, const u8 *mask,
unsigned int vni, unsigned int vni_mask,
u8 dip_hit, u8 lookup_type, bool sleep_ok);
int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
int idx, bool sleep_ok);
int cxgb4_free_raw_mac_filt(struct adapter *adap,
unsigned int viid,
const u8 *addr,
const u8 *mask,
unsigned int idx,
u8 lookup_type,
u8 port_id,
bool sleep_ok);
int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
unsigned int viid,
const u8 *addr,
const u8 *mask,
unsigned int idx,
u8 lookup_type,
u8 port_id,
bool sleep_ok);
int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
int *tcam_idx, const u8 *addr,
bool persistent, u8 *smt_idx);
#endif /* __CXGB4_H__ */

8
drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
View File

@ -727,10 +727,8 @@ void clear_filter(struct adapter *adap, struct filter_entry *f)
cxgb4_smt_release(f->smt);
if (f->fs.val.encap_vld && f->fs.val.ovlan_vld)
if (atomic_dec_and_test(&adap->mps_encap[f->fs.val.ovlan &
0x1ff].refcnt))
t4_free_encap_mac_filt(adap, pi->viid,
f->fs.val.ovlan & 0x1ff, 0);
t4_free_encap_mac_filt(adap, pi->viid,
f->fs.val.ovlan & 0x1ff, 0);
if ((f->fs.hash || is_t6(adap->params.chip)) && f->fs.type)
cxgb4_clip_release(f->dev, (const u32 *)&f->fs.val.lip, 1);
@ -1177,7 +1175,6 @@ static int cxgb4_set_hash_filter(struct net_device *dev,
if (ret < 0)
goto free_atid;
atomic_inc(&adapter->mps_encap[ret].refcnt);
f->fs.val.ovlan = ret;
f->fs.mask.ovlan = 0xffff;
f->fs.val.ovlan_vld = 1;
@ -1420,7 +1417,6 @@ int __cxgb4_set_filter(struct net_device *dev, int filter_id,
if (ret < 0)
goto free_clip;
atomic_inc(&adapter->mps_encap[ret].refcnt);
f->fs.val.ovlan = ret;
f->fs.mask.ovlan = 0x1ff;
f->fs.val.ovlan_vld = 1;

40
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
View File

@ -366,13 +366,19 @@ static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
int ret;
u64 mhash = 0;
u64 uhash = 0;
/* idx stores the index of allocated filters,
* its size should be modified based on the number of
* MAC addresses that we allocate filters for
*/
u16 idx[1] = {};
bool free = false;
bool ucast = is_unicast_ether_addr(mac_addr);
const u8 *maclist[1] = {mac_addr};
struct hash_mac_addr *new_entry;
ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
NULL, ucast ? &uhash : &mhash, false);
ret = cxgb4_alloc_mac_filt(adap, pi->viid, free, 1, maclist,
idx, ucast ? &uhash : &mhash, false);
if (ret < 0)
goto out;
/* if hash != 0, then add the addr to hash addr list
@ -410,7 +416,7 @@ static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
}
}
ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
ret = cxgb4_free_mac_filt(adap, pi->viid, 1, maclist, false);
return ret < 0 ? -EINVAL : 0;
}
@ -449,9 +455,9 @@ static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
* Addresses are programmed to hash region, if tcam runs out of entries.
*
*/
static int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
int *tcam_idx, const u8 *addr, bool persist,
u8 *smt_idx)
int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
int *tcam_idx, const u8 *addr, bool persist,
u8 *smt_idx)
{
struct adapter *adapter = pi->adapter;
struct hash_mac_addr *entry, *new_entry;
@ -505,8 +511,8 @@ static int link_start(struct net_device *dev)
ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
!!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
if (ret == 0)
ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
dev->dev_addr, true, &pi->smt_idx);
ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
dev->dev_addr, true, &pi->smt_idx);
if (ret == 0)
ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
&pi->link_cfg);
@ -3020,8 +3026,8 @@ static int cxgb_set_mac_addr(struct net_device *dev, void *p)
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
addr->sa_data, true, &pi->smt_idx);
ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
addr->sa_data, true, &pi->smt_idx);
if (ret < 0)
return ret;
@ -3273,8 +3279,6 @@ static void cxgb_del_udp_tunnel(struct net_device *netdev,
i);
return;
}
atomic_dec(&adapter->mps_encap[adapter->rawf_start +
pi->port_id].refcnt);
}
}
@ -3363,7 +3367,6 @@ static void cxgb_add_udp_tunnel(struct net_device *netdev,
cxgb_del_udp_tunnel(netdev, ti);
return;
}
atomic_inc(&adapter->mps_encap[ret].refcnt);
}
}
@ -5446,7 +5449,6 @@ static void free_some_resources(struct adapter *adapter)
{
unsigned int i;
kvfree(adapter->mps_encap);
kvfree(adapter->smt);
kvfree(adapter->l2t);
kvfree(adapter->srq);
@ -5972,12 +5974,6 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
adapter->params.offload = 0;
}
adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size,
sizeof(struct mps_encap_entry),
GFP_KERNEL);
if (!adapter->mps_encap)
dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n");
#if IS_ENABLED(CONFIG_IPV6)
if (chip_ver <= CHELSIO_T5 &&
(!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
@ -6053,6 +6049,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
/* check for PCI Express bandwidth capabiltites */
pcie_print_link_status(pdev);
cxgb4_init_mps_ref_entries(adapter);
err = init_rss(adapter);
if (err)
goto out_free_dev;
@ -6179,6 +6177,8 @@ static void remove_one(struct pci_dev *pdev)
disable_interrupts(adapter);
cxgb4_free_mps_ref_entries(adapter);
for_each_port(adapter, i)
if (adapter->port[i]->reg_state == NETREG_REGISTERED)
unregister_netdev(adapter->port[i]);

241
drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c 100644
View File

@ -0,0 +1,241 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019 Chelsio Communications, Inc. All rights reserved. */
#include "cxgb4.h"
static int cxgb4_mps_ref_dec_by_mac(struct adapter *adap,
const u8 *addr, const u8 *mask)
{
u8 bitmask[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
struct mps_entries_ref *mps_entry, *tmp;
int ret = -EINVAL;
spin_lock_bh(&adap->mps_ref_lock);
list_for_each_entry_safe(mps_entry, tmp, &adap->mps_ref, list) {
if (ether_addr_equal(mps_entry->addr, addr) &&
ether_addr_equal(mps_entry->mask, mask ? mask : bitmask)) {
if (!refcount_dec_and_test(&mps_entry->refcnt)) {
spin_unlock_bh(&adap->mps_ref_lock);
return -EBUSY;
}
list_del(&mps_entry->list);
kfree(mps_entry);
ret = 0;
break;
}
}
spin_unlock_bh(&adap->mps_ref_lock);
return ret;
}
static int cxgb4_mps_ref_dec(struct adapter *adap, u16 idx)
{
struct mps_entries_ref *mps_entry, *tmp;
int ret = -EINVAL;
spin_lock(&adap->mps_ref_lock);
list_for_each_entry_safe(mps_entry, tmp, &adap->mps_ref, list) {
if (mps_entry->idx == idx) {
if (!refcount_dec_and_test(&mps_entry->refcnt)) {
spin_unlock(&adap->mps_ref_lock);
return -EBUSY;
}
list_del(&mps_entry->list);
kfree(mps_entry);
ret = 0;
break;
}
}
spin_unlock(&adap->mps_ref_lock);
return ret;
}
static int cxgb4_mps_ref_inc(struct adapter *adap, const u8 *mac_addr,
u16 idx, const u8 *mask)
{
u8 bitmask[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
struct mps_entries_ref *mps_entry;
int ret = 0;
spin_lock_bh(&adap->mps_ref_lock);
list_for_each_entry(mps_entry, &adap->mps_ref, list) {
if (mps_entry->idx == idx) {
refcount_inc(&mps_entry->refcnt);
goto unlock;
}
}
mps_entry = kzalloc(sizeof(*mps_entry), GFP_ATOMIC);
if (!mps_entry) {
ret = -ENOMEM;
goto unlock;
}
ether_addr_copy(mps_entry->mask, mask ? mask : bitmask);
ether_addr_copy(mps_entry->addr, mac_addr);
mps_entry->idx = idx;
refcount_set(&mps_entry->refcnt, 1);
list_add_tail(&mps_entry->list, &adap->mps_ref);
unlock:
spin_unlock_bh(&adap->mps_ref_lock);
return ret;
}
int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
unsigned int naddr, const u8 **addr, bool sleep_ok)
{
int ret, i;
for (i = 0; i < naddr; i++) {
if (!cxgb4_mps_ref_dec_by_mac(adap, addr[i], NULL)) {
ret = t4_free_mac_filt(adap, adap->mbox, viid,
1, &addr[i], sleep_ok);
if (ret < 0)
return ret;
}
}
/* return number of filters freed */
return naddr;
}
int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
bool free, unsigned int naddr, const u8 **addr,
u16 *idx, u64 *hash, bool sleep_ok)
{
int ret, i;
ret = t4_alloc_mac_filt(adap, adap->mbox, viid, free,
naddr, addr, idx, hash, sleep_ok);
if (ret < 0)
return ret;
for (i = 0; i < naddr; i++) {
if (idx[i] != 0xffff) {
if (cxgb4_mps_ref_inc(adap, addr[i], idx[i], NULL)) {
ret = -ENOMEM;
goto error;
}
}
}
goto out;
error:
cxgb4_free_mac_filt(adap, viid, naddr, addr, sleep_ok);
out:
/* Returns a negative error number or the number of filters allocated */
return ret;
}
int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
int *tcam_idx, const u8 *addr,
bool persistent, u8 *smt_idx)
{
int ret;
ret = cxgb4_change_mac(pi, viid, tcam_idx,
addr, persistent, smt_idx);
if (ret < 0)
return ret;
cxgb4_mps_ref_inc(pi->adapter, addr, *tcam_idx, NULL);
return ret;
}
int cxgb4_free_raw_mac_filt(struct adapter *adap,
unsigned int viid,
const u8 *addr,
const u8 *mask,
unsigned int idx,
u8 lookup_type,
u8 port_id,
bool sleep_ok)
{
int ret = 0;
if (!cxgb4_mps_ref_dec(adap, idx))
ret = t4_free_raw_mac_filt(adap, viid, addr,
mask, idx, lookup_type,
port_id, sleep_ok);
return ret;
}
int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
unsigned int viid,
const u8 *addr,
const u8 *mask,
unsigned int idx,
u8 lookup_type,
u8 port_id,
bool sleep_ok)
{
int ret;
ret = t4_alloc_raw_mac_filt(adap, viid, addr,
mask, idx, lookup_type,
port_id, sleep_ok);
if (ret < 0)
return ret;
if (cxgb4_mps_ref_inc(adap, addr, ret, mask)) {
ret = -ENOMEM;
t4_free_raw_mac_filt(adap, viid, addr,
mask, idx, lookup_type,
port_id, sleep_ok);
}
return ret;
}
int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
int idx, bool sleep_ok)
{
int ret = 0;
if (!cxgb4_mps_ref_dec(adap, idx))
ret = t4_free_encap_mac_filt(adap, viid, idx, sleep_ok);
return ret;
}
int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
const u8 *addr, const u8 *mask,
unsigned int vni, unsigned int vni_mask,
u8 dip_hit, u8 lookup_type, bool sleep_ok)
{
int ret;
ret = t4_alloc_encap_mac_filt(adap, viid, addr, mask, vni, vni_mask,
dip_hit, lookup_type, sleep_ok);
if (ret < 0)
return ret;
if (cxgb4_mps_ref_inc(adap, addr, ret, mask)) {
ret = -ENOMEM;
t4_free_encap_mac_filt(adap, viid, ret, sleep_ok);
}
return ret;
}
int cxgb4_init_mps_ref_entries(struct adapter *adap)
{
spin_lock_init(&adap->mps_ref_lock);
INIT_LIST_HEAD(&adap->mps_ref);
return 0;
}
void cxgb4_free_mps_ref_entries(struct adapter *adap)
{
struct mps_entries_ref *mps_entry, *tmp;
if (!list_empty(&adap->mps_ref))
return;
spin_lock(&adap->mps_ref_lock);
list_for_each_entry_safe(mps_entry, tmp, &adap->mps_ref, list) {
list_del(&mps_entry->list);
kfree(mps_entry);
}
spin_unlock(&adap->mps_ref_lock);
}