PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
This PCIe controller is based on the Mobiveil GPEX IP, it work in EP mode if select this config opteration. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> [Zhiqiang: Correct the Copyright] Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>5.4-rM2-2.2.x-imx-squashed
Xiaowei Bao
Dong Aisheng
parent
924bfdb0f7
commit
04f8a74d2a
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@ -12436,11 +12436,13 @@ F: drivers/pci/controller/dwc/*layerscape*
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PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
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M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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M: Xiaowei Bao <xiaowei.bao@nxp.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
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F: drivers/pci/controller/mobibeil/pcie-layerscape-gen4.c
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F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
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PCI DRIVER FOR GENERIC OF HOSTS
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M: Will Deacon <will@kernel.org>
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@ -27,13 +27,24 @@ config PCIE_MOBIVEIL_PLAT
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for address translation and it is a PCIe Gen4 IP.
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config PCIE_LAYERSCAPE_GEN4
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bool "Freescale Layerscape PCIe Gen4 controller"
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bool "Freescale Layerscpe PCIe Gen4 controller in RC mode"
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depends on PCI
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depends on OF && (ARM64 || ARCH_LAYERSCAPE)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_MOBIVEIL_HOST
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help
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Say Y here if you want PCIe Gen4 controller support on
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Layerscape SoCs. The PCIe controller can work in RC or
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EP mode according to RCW[HOST_AGT_PEX] setting.
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Layerscape SoCs. And the PCIe controller work in RC mode
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by setting the RCW[HOST_AGT_PEX] to 0.
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config PCIE_LAYERSCAPE_GEN4_EP
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bool "Freescale Layerscpe PCIe Gen4 controller in EP mode"
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depends on PCI
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depends on OF && (ARM64 || ARCH_LAYERSCAPE)
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depends on PCI_ENDPOINT
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select PCIE_MOBIVEIL_EP
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help
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Say Y here if you want PCIe Gen4 controller support on
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Layerscape SoCs. And the PCIe controller work in EP mode
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by setting the RCW[HOST_AGT_PEX] to 1.
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endmenu
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@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
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obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
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obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
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obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
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obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4_EP) += pcie-layerscape-gen4-ep.o
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@ -0,0 +1,156 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe controller EP driver for Freescale Layerscape SoCs
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*
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* Copyright 2019 NXP
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*
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* Author: Xiaowei Bao <xiaowei.bao@nxp.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include "pcie-mobiveil.h"
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#define PCIE_LX2_BAR_NUM 4
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#define to_ls_pcie_g4_ep(x) dev_get_drvdata((x)->dev)
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struct ls_pcie_g4_ep {
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struct mobiveil_pcie *mv_pci;
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};
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static const struct of_device_id ls_pcie_g4_ep_of_match[] = {
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{ .compatible = "fsl,lx2160a-pcie-ep",},
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{ },
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};
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static const struct pci_epc_features ls_pcie_g4_epc_features = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = true,
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.reserved_bar = (1 << BAR_4) | (1 << BAR_5),
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};
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static const struct pci_epc_features*
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ls_pcie_g4_ep_get_features(struct mobiveil_pcie_ep *ep)
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{
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return &ls_pcie_g4_epc_features;
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}
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static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
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{
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struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
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int win_idx;
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u8 bar;
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ep->bar_num = PCIE_LX2_BAR_NUM;
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for (bar = BAR_0; bar < ep->epc->max_functions * ep->bar_num; bar++)
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mobiveil_pcie_ep_reset_bar(mv_pci, bar);
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for (win_idx = 0; win_idx < ep->apio_wins; win_idx++)
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mobiveil_pcie_disable_ob_win(mv_pci, win_idx);
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}
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static int ls_pcie_g4_ep_raise_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type,
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u16 interrupt_num)
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{
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struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
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return mobiveil_pcie_ep_raise_legacy_irq(ep, func_no);
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case PCI_EPC_IRQ_MSI:
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return mobiveil_pcie_ep_raise_msi_irq(ep, func_no,
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interrupt_num);
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case PCI_EPC_IRQ_MSIX:
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return mobiveil_pcie_ep_raise_msix_irq(ep, func_no,
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interrupt_num);
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default:
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dev_err(&mv_pci->pdev->dev, "UNKNOWN IRQ type\n");
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}
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return 0;
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}
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static const struct mobiveil_pcie_ep_ops pcie_ep_ops = {
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.ep_init = ls_pcie_g4_ep_init,
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.raise_irq = ls_pcie_g4_ep_raise_irq,
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.get_features = ls_pcie_g4_ep_get_features,
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};
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static int __init ls_pcie_gen4_add_pcie_ep(struct ls_pcie_g4_ep *ls_ep,
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struct platform_device *pdev)
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{
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struct mobiveil_pcie *mv_pci = ls_ep->mv_pci;
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struct device *dev = &pdev->dev;
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struct mobiveil_pcie_ep *ep;
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struct resource *res;
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int ret;
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ep = &mv_pci->ep;
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ep->ops = &pcie_ep_ops;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = mobiveil_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize layerscape endpoint\n");
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return ret;
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}
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return 0;
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}
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static int __init ls_pcie_g4_ep_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mobiveil_pcie *mv_pci;
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struct ls_pcie_g4_ep *ls_ep;
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struct resource *res;
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int ret;
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ls_ep = devm_kzalloc(dev, sizeof(*ls_ep), GFP_KERNEL);
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if (!ls_ep)
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return -ENOMEM;
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mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
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if (!mv_pci)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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mv_pci->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(mv_pci->csr_axi_slave_base))
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return PTR_ERR(mv_pci->csr_axi_slave_base);
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mv_pci->pdev = pdev;
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ls_ep->mv_pci = mv_pci;
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platform_set_drvdata(pdev, ls_ep);
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ret = ls_pcie_gen4_add_pcie_ep(ls_ep, pdev);
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return ret;
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}
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static struct platform_driver ls_pcie_g4_ep_driver = {
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.driver = {
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.name = "layerscape-pcie-gen4-ep",
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.of_match_table = ls_pcie_g4_ep_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver_probe(ls_pcie_g4_ep_driver, ls_pcie_g4_ep_probe);
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