drm/amdgpu: Fixed missing to clear some EDC count
EDC counts are related to instance and se. They are not the same for different type of EDC. EDC clearing are changed to base on individual EDC's instance and SE number. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>alistair/sunxi64-5.4-dsi
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59648d6954
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052af915d8
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@ -3586,37 +3586,38 @@ static const struct soc15_reg_entry sgpr_init_regs[] = {
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};
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static const struct soc15_reg_entry sec_ded_counter_registers[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED) },
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{ SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6},
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6},
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1},
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{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32},
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{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32},
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{ SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72},
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{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
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{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
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{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
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};
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static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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@ -3624,7 +3625,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
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struct amdgpu_ib ib;
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struct dma_fence *f = NULL;
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int r, i, j;
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int r, i, j, k;
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unsigned total_size, vgpr_offset, sgpr_offset;
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u64 gpu_addr;
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@ -3736,19 +3737,13 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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/* read back registers to clear the counters */
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mutex_lock(&adev->grbm_idx_mutex);
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for (j = 0; j < 16; j++) {
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gfx_v9_0_select_se_sh(adev, 0x01, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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gfx_v9_0_select_se_sh(adev, 0x02, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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gfx_v9_0_select_se_sh(adev, 0x03, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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gfx_v9_0_select_se_sh(adev, 0x04, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) {
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for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) {
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for (k = 0; k < sec_ded_counter_registers[i].instance; k++) {
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gfx_v9_0_select_se_sh(adev, j, 0x0, k);
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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}
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}
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}
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WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
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mutex_unlock(&adev->grbm_idx_mutex);
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@ -48,6 +48,8 @@ struct soc15_reg_entry {
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uint32_t seg;
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uint32_t reg_offset;
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uint32_t reg_value;
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uint32_t se_num;
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uint32_t instance;
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};
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#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
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