Assign a dedicated feature word to a CPUID leaf which is widely used.
-----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmAqYMkACgkQEsHwGGHe VUoK8Q//SzA9l3eUb8y3V0bezrwFysR0K9bgsKaSHNvbPiJQpFmQsLgysnqF5+Fp jqJyq8aCYa4JfOwuJZhIrtMiIPFMUw4iNafgj6arLs0V1sdQCmSMwWj5ODnVQ0gn H5LwYwCzLtXuiA7Ka6wSaw/FJWRF/e+G4ZVgENpz+JSZ5KlsmCh8rckMNmmdelM/ nq9ilJmua+gW96lT7ompurcpWZeSaMVlBgLmslXU4wh/O6ZegkkP3e0RNgTPq1ge kvHzqAEMt58CsY2aMuwkMjpoSNDesdF0Z8VahQ40XY5tBw5w+EjZ9cF3stXwDBfN 0zSMd7mZtI/mzG0EQkrqxEqQJIH5pvKk0dG18aV/QTjX27OJbvu9B2+0HpIxlMCB 1OUAk6nnOXp+zoH4bEQeHURJrymFUyRhwDpxZ8uGvZjaWjfQdDt6fhi6hqmeXOs8 iab3x+9+QM0x7TOtzCv7kqV18kKftX9A7Nl14v0EcpO6nNtbh+ac1zcad+rmTCAg gGBBP60ESH9VK1TWTEX94YW67M96El2OeEIEUihD7pxO0J5GQZL8ZUBXsJXl7oIn 95+BUKnczJUj4CAG1dHRx3lko1OcfxOikOGjFv4TALF+tb/S0Rvn0cE+AGY1DWA6 1b9zdFFYsLyUXO2C29IL3tlCKrcQdf8OzI+S4ehw1gGYxA7x8QA= =XADP -----END PGP SIGNATURE----- Merge tag 'x86_cpu_for_v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 CPUID cleanup from Borislav Petkov: "Assign a dedicated feature word to a CPUID leaf which is widely used" * tag 'x86_cpu_for_v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpufeatures: Assign dedicated feature word for CPUID_0x8000001F[EAX]master
Linus Torvalds
commit
0570b69305
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@ -30,6 +30,7 @@ enum cpuid_leafs
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CPUID_7_ECX,
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CPUID_8000_0007_EBX,
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CPUID_7_EDX,
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CPUID_8000_001F_EAX,
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};
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#ifdef CONFIG_X86_FEATURE_NAMES
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@ -88,8 +89,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \
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REQUIRED_MASK_CHECK || \
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BUILD_BUG_ON_ZERO(NCAPINTS != 19))
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BUILD_BUG_ON_ZERO(NCAPINTS != 20))
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#define DISABLED_MASK_BIT_SET(feature_bit) \
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( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
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@ -111,8 +113,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \
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DISABLED_MASK_CHECK || \
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BUILD_BUG_ON_ZERO(NCAPINTS != 19))
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BUILD_BUG_ON_ZERO(NCAPINTS != 20))
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#define cpu_has(c, bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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@ -13,7 +13,7 @@
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/*
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* Defines x86 CPU feature bits
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*/
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#define NCAPINTS 19 /* N 32-bit words worth of info */
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#define NCAPINTS 20 /* N 32-bit words worth of info */
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#define NBUGINTS 1 /* N 32-bit bug flags */
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/*
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@ -96,7 +96,7 @@
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#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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#define X86_FEATURE_SME_COHERENT ( 3*32+17) /* "" AMD hardware-enforced cache coherency */
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/* FREE! ( 3*32+17) */
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#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
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#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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@ -201,7 +201,7 @@
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#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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/* FREE! ( 7*32+10) */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
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@ -211,7 +211,7 @@
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#define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
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#define X86_FEATURE_SEV ( 7*32+20) /* AMD Secure Encrypted Virtualization */
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/* FREE! ( 7*32+20) */
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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@ -236,8 +236,6 @@
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#define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
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#define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
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#define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
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#define X86_FEATURE_SEV_ES ( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
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#define X86_FEATURE_VM_PAGE_FLUSH ( 8*32+21) /* "" VM Page Flush MSR is supported */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
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#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
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@ -385,6 +383,13 @@
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#define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
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#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
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/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
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#define X86_FEATURE_SME (19*32+ 0) /* AMD Secure Memory Encryption */
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#define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */
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#define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */
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#define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
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#define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
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/*
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* BUG word(s)
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*/
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@ -91,6 +91,7 @@
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DISABLE_ENQCMD)
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#define DISABLED_MASK17 0
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#define DISABLED_MASK18 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#define DISABLED_MASK19 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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@ -101,6 +101,7 @@
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#define REQUIRED_MASK16 0
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#define REQUIRED_MASK17 0
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#define REQUIRED_MASK19 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */
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@ -960,6 +960,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
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if (c->extended_cpuid_level >= 0x8000000a)
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c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
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if (c->extended_cpuid_level >= 0x8000001f)
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c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
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init_scattered_cpuid_features(c);
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init_speculation_control(c);
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@ -40,11 +40,6 @@ static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
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{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
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{ X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 },
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{ X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 },
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{ X86_FEATURE_SEV_ES, CPUID_EAX, 3, 0x8000001f, 0 },
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{ X86_FEATURE_SME_COHERENT, CPUID_EAX, 10, 0x8000001f, 0 },
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{ X86_FEATURE_VM_PAGE_FLUSH, CPUID_EAX, 2, 0x8000001f, 0 },
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{ 0, 0, 0, 0, 0 }
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};
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@ -91,6 +91,7 @@
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DISABLE_ENQCMD)
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#define DISABLED_MASK17 0
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#define DISABLED_MASK18 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#define DISABLED_MASK19 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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@ -101,6 +101,7 @@
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#define REQUIRED_MASK16 0
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#define REQUIRED_MASK17 0
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#define REQUIRED_MASK19 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */
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