drm/i915/bxt: add missing DDI PLL registers to the state checking
Although we have a fixed setting for the PLL9 and EBB4 registers, it still makes sense to check them together with the rest of PLL registers. While at it also remove a redundant comment about 10 bit clock enabling. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -372,7 +372,8 @@ struct intel_dpll_hw_state {
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uint32_t cfgcr1, cfgcr2;
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uint32_t cfgcr1, cfgcr2;
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/* bxt */
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/* bxt */
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uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
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uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
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pcsdw12;
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};
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};
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struct intel_shared_dpll_config {
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struct intel_shared_dpll_config {
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@ -1208,7 +1208,8 @@ enum skl_disp_power_wells {
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/* PORT_PLL_8_A */
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/* PORT_PLL_8_A */
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#define PORT_PLL_TARGET_CNT_MASK 0x3FF
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#define PORT_PLL_TARGET_CNT_MASK 0x3FF
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/* PORT_PLL_9_A */
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/* PORT_PLL_9_A */
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#define PORT_PLL_LOCK_THRESHOLD_MASK 0xe
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#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
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#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
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/* PORT_PLL_10_A */
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/* PORT_PLL_10_A */
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#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
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#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
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#define PORT_PLL_DCO_AMP_MASK 0x3c00
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#define PORT_PLL_DCO_AMP_MASK 0x3c00
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@ -1722,11 +1722,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
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crtc_state->dpll_hw_state.pll8 = targ_cnt;
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crtc_state->dpll_hw_state.pll8 = targ_cnt;
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crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
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if (dcoampovr_en_h)
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if (dcoampovr_en_h)
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crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
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crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
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crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
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crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
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crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
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crtc_state->dpll_hw_state.pcsdw12 =
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crtc_state->dpll_hw_state.pcsdw12 =
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LANESTAGGER_STRAP_OVRD | lanestagger;
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LANESTAGGER_STRAP_OVRD | lanestagger;
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@ -2767,7 +2771,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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temp = I915_READ(BXT_PORT_PLL(port, 9));
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temp = I915_READ(BXT_PORT_PLL(port, 9));
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temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
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temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
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temp |= (5 << 1);
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temp |= pll->config.hw_state.pll9;
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I915_WRITE(BXT_PORT_PLL(port, 9), temp);
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I915_WRITE(BXT_PORT_PLL(port, 9), temp);
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temp = I915_READ(BXT_PORT_PLL(port, 10));
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temp = I915_READ(BXT_PORT_PLL(port, 10));
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@ -2780,8 +2784,8 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
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temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
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temp |= PORT_PLL_RECALIBRATE;
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temp |= PORT_PLL_RECALIBRATE;
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I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
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I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
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/* Enable 10 bit clock */
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temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
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temp |= PORT_PLL_10BIT_CLK_ENABLE;
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temp |= pll->config.hw_state.ebb4;
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I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
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I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
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/* Enable PLL */
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/* Enable PLL */
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@ -2832,12 +2836,18 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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return false;
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return false;
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hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
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hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
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hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
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hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
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hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
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hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
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hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
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hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
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hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
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hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
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hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
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hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
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hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
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hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
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hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
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hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
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hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
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hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
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hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
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hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
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/*
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/*
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* While we write to the group register to program all lanes at once we
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* While we write to the group register to program all lanes at once we
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@ -12012,17 +12012,19 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
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DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
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DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
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if (IS_BROXTON(dev)) {
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if (IS_BROXTON(dev)) {
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DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
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DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
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"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
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"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
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"pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
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"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pcsdw12: 0x%x\n",
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pipe_config->ddi_pll_sel,
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pipe_config->ddi_pll_sel,
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pipe_config->dpll_hw_state.ebb0,
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pipe_config->dpll_hw_state.ebb0,
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pipe_config->dpll_hw_state.ebb4,
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pipe_config->dpll_hw_state.pll0,
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pipe_config->dpll_hw_state.pll0,
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pipe_config->dpll_hw_state.pll1,
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pipe_config->dpll_hw_state.pll1,
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pipe_config->dpll_hw_state.pll2,
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pipe_config->dpll_hw_state.pll2,
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pipe_config->dpll_hw_state.pll3,
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pipe_config->dpll_hw_state.pll3,
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pipe_config->dpll_hw_state.pll6,
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pipe_config->dpll_hw_state.pll6,
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pipe_config->dpll_hw_state.pll8,
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pipe_config->dpll_hw_state.pll8,
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pipe_config->dpll_hw_state.pll9,
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pipe_config->dpll_hw_state.pcsdw12);
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pipe_config->dpll_hw_state.pcsdw12);
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} else if (IS_SKYLAKE(dev)) {
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} else if (IS_SKYLAKE(dev)) {
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DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
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DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
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