drm/radeon/kms: Update evergreen functions for trinity
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1328,7 +1328,10 @@ void evergreen_mc_program(struct radeon_device *rdev)
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rdev->mc.vram_end >> 12);
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rdev->mc.vram_end >> 12);
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}
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}
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
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if (rdev->flags & RADEON_IS_IGP) {
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/* llano/ontario only */
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if ((rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2)) {
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tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
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tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
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tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
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tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
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tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
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tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
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@ -1972,7 +1975,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
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mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
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if (rdev->flags & RADEON_IS_IGP)
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if ((rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2))
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mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
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mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
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else
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else
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mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
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mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
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@ -2362,7 +2367,9 @@ int evergreen_mc_init(struct radeon_device *rdev)
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/* Get VRAM informations */
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/* Get VRAM informations */
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rdev->mc.vram_is_ddr = true;
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rdev->mc.vram_is_ddr = true;
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if (rdev->flags & RADEON_IS_IGP)
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if ((rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2))
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tmp = RREG32(FUS_MC_ARB_RAMCFG);
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tmp = RREG32(FUS_MC_ARB_RAMCFG);
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else
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else
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tmp = RREG32(MC_ARB_RAMCFG);
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tmp = RREG32(MC_ARB_RAMCFG);
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@ -2394,12 +2401,14 @@ int evergreen_mc_init(struct radeon_device *rdev)
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rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
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rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
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rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
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rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
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/* Setup GPU memory space */
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/* Setup GPU memory space */
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if (rdev->flags & RADEON_IS_IGP) {
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if ((rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2)) {
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/* size in bytes on fusion */
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/* size in bytes on fusion */
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
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} else {
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} else {
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/* size in MB on evergreen */
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/* size in MB on evergreen/cayman/tn */
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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}
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}
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@ -2557,7 +2566,9 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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}
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}
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WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
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/* only one DAC on DCE6 */
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if (!ASIC_IS_DCE6(rdev))
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WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
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WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
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WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
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tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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@ -106,6 +106,7 @@
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#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
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#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
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#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
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#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
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#define FUS_MC_VM_FB_OFFSET 0x2068
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#define MC_SHARED_BLACKOUT_CNTL 0x20ac
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#define MC_SHARED_BLACKOUT_CNTL 0x20ac
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#define MC_ARB_RAMCFG 0x2760
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#define MC_ARB_RAMCFG 0x2760
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