drm/dsc: Add kernel documentation for DRM DP DSC helpers
This patch adds appropriate kernel documentation for DRM DP helpers used for enabling Display Stream compression functionality in drm_dp_helper.h and drm_dp_helper.c as well as for the DSC spec related structure definitions and helpers in drm_dsc.c and drm_dsc.h Also add links between the functions and structures in the documentation. v3: * Fix the checkpatch warnings (Sean Paul) v2: * Add inline comments for longer structs (Daniel Vetter) * Split the summary and description (Daniel Vetter) Suggested-by: Daniel Vetter <daniel.vetter@intel.com> Suggested-by: Sean Paul <sean@poorly.run> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Sean Paul <sean@poorly.run> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Acked-by: Sean Paul <sean@poorly.run> Reviewed-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190206213148.21390-1-manasi.d.navare@intel.comhifive-unleashed-5.1
Manasi Navare
parent
05f8bc82fc
commit
05bad2357a
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@ -1360,7 +1360,20 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
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EXPORT_SYMBOL(drm_dp_read_desc);
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/**
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* DRM DP Helpers for DSC
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* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
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* supported by the DSC sink.
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* @dsc_dpcd: DSC capabilities from DPCD
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* @is_edp: true if its eDP, false for DP
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*
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* Read the slice capabilities DPCD register from DSC sink to get
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* the maximum slice count supported. This is used to populate
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* the DSC parameters in the &struct drm_dsc_config by the driver.
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* Driver creates an infoframe using these parameters to populate
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* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
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* infoframe using the helper function drm_dsc_pps_infoframe_pack()
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*
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* Returns:
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* Maximum slice count supported by DSC sink or 0 its invalid
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*/
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u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
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bool is_edp)
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@ -1405,6 +1418,21 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
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}
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EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
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/**
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* drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
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* @dsc_dpcd: DSC capabilities from DPCD
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*
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* Read the DSC DPCD register to parse the line buffer depth in bits which is
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* number of bits of precision within the decoder line buffer supported by
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* the DSC sink. This is used to populate the DSC parameters in the
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* &struct drm_dsc_config by the driver.
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* Driver creates an infoframe using these parameters to populate
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* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
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* infoframe using the helper function drm_dsc_pps_infoframe_pack()
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*
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* Returns:
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* Line buffer depth supported by DSC panel or 0 its invalid
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*/
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u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
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{
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u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
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@ -1434,6 +1462,23 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
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}
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EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
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/**
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* drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
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* values supported by the DSC sink.
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* @dsc_dpcd: DSC capabilities from DPCD
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* @dsc_bpc: An array to be filled by this helper with supported
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* input bpcs.
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*
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* Read the DSC DPCD from the sink device to parse the supported bits per
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* component values. This is used to populate the DSC parameters
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* in the &struct drm_dsc_config by the driver.
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* Driver creates an infoframe using these parameters to populate
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* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
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* infoframe using the helper function drm_dsc_pps_infoframe_pack()
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*
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* Returns:
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* Number of input BPC values parsed from the DPCD
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*/
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int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
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u8 dsc_bpc[3])
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{
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@ -17,6 +17,12 @@
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/**
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* DOC: dsc helpers
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*
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* VESA specification for DP 1.4 adds a new feature called Display Stream
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* Compression (DSC) used to compress the pixel bits before sending it on
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* DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
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* display interfaces can support high resolutions at higher frames rates uisng
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* the maximum available link capacity of these interfaces.
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*
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* These functions contain some common logic and helpers to deal with VESA
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* Display Stream Compression standard required for DSC on Display Port/eDP or
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* MIPI display interfaces.
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@ -26,6 +32,13 @@
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* drm_dsc_dp_pps_header_init() - Initializes the PPS Header
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* for DisplayPort as per the DP 1.4 spec.
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* @pps_sdp: Secondary data packet for DSC Picture Parameter Set
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* as defined in &struct drm_dsc_pps_infoframe
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*
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* DP 1.4 spec defines the secondary data packet for sending the
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* picture parameter infoframes from the source to the sink.
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* This function populates the pps header defined in
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* &struct drm_dsc_pps_infoframe as per the header bytes defined
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* in &struct dp_sdp_header.
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*/
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void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
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{
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@ -38,15 +51,20 @@ EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
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/**
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* drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
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* using the DSC configuration parameters in the order expected
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* by the DSC Display Sink device. For the DSC, the sink device
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* expects the PPS payload in the big endian format for the fields
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* that span more than 1 byte.
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*
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* @pps_sdp:
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* Secondary data packet for DSC Picture Parameter Set
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* Secondary data packet for DSC Picture Parameter Set. This is defined
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* by &struct drm_dsc_pps_infoframe
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* @dsc_cfg:
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* DSC Configuration data filled by driver
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* DSC Configuration data filled by driver as defined by
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* &struct drm_dsc_config
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*
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* DSC source device sends a secondary data packet filled with all the
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* picture parameter set (PPS) information required by the sink to decode
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* the compressed frame. Driver populates the dsC PPS infoframe using the DSC
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* configuration parameters in the order expected by the DSC Display Sink
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* device. For the DSC, the sink device expects the PPS payload in the big
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* endian format for the fields that span more than 1 byte.
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*/
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void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
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const struct drm_dsc_config *dsc_cfg)
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@ -1052,11 +1052,18 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw);
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#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
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/* 0x80+ CEA-861 infoframe types */
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/**
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* struct dp_sdp_header - DP secondary data packet header
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* @HB0: Secondary Data Packet ID
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* @HB1: Secondary Data Packet Type
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* @HB2: Secondary Data Packet Specific header, Byte 0
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* @HB3: Secondary Data packet Specific header, Byte 1
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*/
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struct dp_sdp_header {
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u8 HB0; /* Secondary Data Packet ID */
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u8 HB1; /* Secondary Data Packet Type */
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u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */
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u8 HB3; /* Secondary Data packet Specific header, Byte 1 */
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u8 HB0;
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u8 HB1;
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u8 HB2;
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u8 HB3;
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} __packed;
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#define EDP_SDP_HEADER_REVISION_MASK 0x1F
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@ -44,111 +44,231 @@
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#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
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#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
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/* Configuration for a single Rate Control model range */
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/**
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* struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
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*
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* This defines different rate control parameters used by the DSC engine
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* to compress the frame.
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*/
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struct drm_dsc_rc_range_parameters {
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/* Min Quantization Parameters allowed for this range */
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/**
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* @range_min_qp: Min Quantization Parameters allowed for this range
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*/
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u8 range_min_qp;
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/* Max Quantization Parameters allowed for this range */
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/**
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* @range_max_qp: Max Quantization Parameters allowed for this range
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*/
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u8 range_max_qp;
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/* Bits/group offset to apply to target for this group */
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/**
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* @range_bpg_offset:
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* Bits/group offset to apply to target for this group
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*/
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u8 range_bpg_offset;
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};
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/**
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* struct drm_dsc_config - Parameters required to configure DSC
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*
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* Driver populates this structure with all the parameters required
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* to configure the display stream compression on the source.
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*/
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struct drm_dsc_config {
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/* Bits / component for previous reconstructed line buffer */
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/**
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* @line_buf_depth:
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* Bits per component for previous reconstructed line buffer
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*/
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u8 line_buf_depth;
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/* Bits per component to code (must be 8, 10, or 12) */
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/**
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* @bits_per_component: Bits per component to code (8/10/12)
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*/
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u8 bits_per_component;
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/*
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* Flag indicating to do RGB - YCoCg conversion
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* and back (should be 1 for RGB input)
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/**
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* @convert_rgb:
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* Flag to indicate if RGB - YCoCg conversion is needed
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* True if RGB input, False if YCoCg input
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*/
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bool convert_rgb;
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/**
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* @slice_count: Number fo slices per line used by the DSC encoder
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*/
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u8 slice_count;
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/* Slice Width */
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/**
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* @slice_width: Width of each slice in pixels
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*/
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u16 slice_width;
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/* Slice Height */
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/**
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* @slice_height: Slice height in pixels
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*/
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u16 slice_height;
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/*
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* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
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* outside of DSC encode/decode algorithm)
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/**
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* @enable422: True for 4_2_2 sampling, false for 4_4_4 sampling
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*/
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bool enable422;
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/* Picture Width */
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/**
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* @pic_width: Width of the input display frame in pixels
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*/
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u16 pic_width;
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/* Picture Height */
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/**
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* @pic_height: Vertical height of the input display frame
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*/
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u16 pic_height;
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/* Offset to bits/group used by RC to determine QP adjustment */
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/**
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* @rc_tgt_offset_high:
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* Offset to bits/group used by RC to determine QP adjustment
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*/
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u8 rc_tgt_offset_high;
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/* Offset to bits/group used by RC to determine QP adjustment */
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/**
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* @rc_tgt_offset_low:
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* Offset to bits/group used by RC to determine QP adjustment
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*/
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u8 rc_tgt_offset_low;
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/* Bits/pixel target << 4 (ie., 4 fractional bits) */
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/**
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* @bits_per_pixel:
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* Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
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*/
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u16 bits_per_pixel;
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/*
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* Factor to determine if an edge is present based
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* on the bits produced
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/**
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* @rc_edge_factor:
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* Factor to determine if an edge is present based on the bits produced
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*/
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u8 rc_edge_factor;
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/* Slow down incrementing once the range reaches this value */
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/**
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* @rc_quant_incr_limit1:
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* Slow down incrementing once the range reaches this value
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*/
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u8 rc_quant_incr_limit1;
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/* Slow down incrementing once the range reaches this value */
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/**
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* @rc_quant_incr_limit0:
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* Slow down incrementing once the range reaches this value
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*/
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u8 rc_quant_incr_limit0;
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/* Number of pixels to delay the initial transmission */
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/**
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* @initial_xmit_delay:
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* Number of pixels to delay the initial transmission
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*/
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u16 initial_xmit_delay;
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/* Number of pixels to delay the VLD on the decoder,not including SSM */
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/**
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* @initial_dec_delay:
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* Initial decoder delay, number of pixel times that the decoder
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* accumulates data in its rate buffer before starting to decode
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* and output pixels.
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*/
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u16 initial_dec_delay;
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/* Block prediction enable */
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/**
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* @block_pred_enable:
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* True if block prediction is used to code any groups within the
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* picture. False if BP not used
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*/
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bool block_pred_enable;
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/* Bits/group offset to use for first line of the slice */
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/**
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* @first_line_bpg_offset:
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* Number of additional bits allocated for each group on the first
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* line of slice.
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*/
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u8 first_line_bpg_offset;
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/* Value to use for RC model offset at slice start */
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/**
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* @initial_offset: Value to use for RC model offset at slice start
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*/
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u16 initial_offset;
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/* Thresholds defining each of the buffer ranges */
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/**
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* @rc_buf_thresh: Thresholds defining each of the buffer ranges
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*/
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u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
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/* Parameters for each of the RC ranges */
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/**
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* @rc_range_params:
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* Parameters for each of the RC ranges defined in
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* &struct drm_dsc_rc_range_parameters
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*/
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struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
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/* Total size of RC model */
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/**
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* @rc_model_size: Total size of RC model
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*/
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u16 rc_model_size;
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/* Minimum QP where flatness information is sent */
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/**
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* @flatness_min_qp: Minimum QP where flatness information is sent
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*/
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u8 flatness_min_qp;
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/* Maximum QP where flatness information is sent */
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/**
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* @flatness_max_qp: Maximum QP where flatness information is sent
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*/
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u8 flatness_max_qp;
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/* Initial value for scale factor */
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/**
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* @initial_scale_value: Initial value for the scale factor
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*/
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u8 initial_scale_value;
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/* Decrement scale factor every scale_decrement_interval groups */
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/**
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* @scale_decrement_interval:
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* Specifies number of group times between decrementing the scale factor
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* at beginning of a slice.
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*/
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u16 scale_decrement_interval;
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/* Increment scale factor every scale_increment_interval groups */
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/**
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* @scale_increment_interval:
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* Number of group times between incrementing the scale factor value
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* used at the beginning of a slice.
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*/
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u16 scale_increment_interval;
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/* Non-first line BPG offset to use */
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/**
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* @nfl_bpg_offset: Non first line BPG offset to be used
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*/
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u16 nfl_bpg_offset;
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/* BPG offset used to enforce slice bit */
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/**
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* @slice_bpg_offset: BPG offset used to enforce slice bit
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*/
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u16 slice_bpg_offset;
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/* Final RC linear transformation offset value */
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/**
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* @final_offset: Final RC linear transformation offset value
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*/
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u16 final_offset;
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/* Enable on-off VBR (ie., disable stuffing bits) */
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/**
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* @vbr_enable: True if VBR mode is enabled, false if disabled
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*/
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bool vbr_enable;
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/* Mux word size (in bits) for SSM mode */
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/**
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* @mux_word_size: Mux word size (in bits) for SSM mode
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*/
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u8 mux_word_size;
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/*
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* The (max) size in bytes of the "chunks" that are
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* used in slice multiplexing
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/**
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* @slice_chunk_size:
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* The (max) size in bytes of the "chunks" that are used in slice
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* multiplexing.
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*/
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u16 slice_chunk_size;
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/* Rate Control buffer siz in bits */
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/**
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* @rc_bits: Rate control buffer size in bits
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*/
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u16 rc_bits;
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/* DSC Minor Version */
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/**
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* @dsc_version_minor: DSC minor version
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*/
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u8 dsc_version_minor;
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/* DSC Major version */
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/**
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* @dsc_version_major: DSC major version
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*/
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u8 dsc_version_major;
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/* Native 4:2:2 support */
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/**
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* @native_422: True if Native 4:2:2 supported, else false
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*/
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bool native_422;
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/* Native 4:2:0 support */
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/**
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* @native_420: True if Native 4:2:0 supported else false.
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*/
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bool native_420;
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/* Additional bits/grp for seconnd line of slice for native 4:2:0 */
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/**
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* @second_line_bpg_offset:
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* Additional bits/grp for seconnd line of slice for native 4:2:0
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*/
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u8 second_line_bpg_offset;
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/* Num of bits deallocated for each grp that is not in second line of slice */
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/**
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* @nsl_bpg_offset:
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* Num of bits deallocated for each grp that is not in second line of
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* slice
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*/
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u16 nsl_bpg_offset;
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/* Offset adj fr second line in Native 4:2:0 mode */
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/**
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* @second_line_offset_adj:
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* Offset adjustment for second line in Native 4:2:0 mode
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*/
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u16 second_line_offset_adj;
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};
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||||
|
|
@ -468,10 +588,13 @@ struct drm_dsc_picture_parameter_set {
|
|||
* This structure represents the DSC PPS infoframe required to send the Picture
|
||||
* Parameter Set metadata required before enabling VESA Display Stream
|
||||
* Compression. This is based on the DP Secondary Data Packet structure and
|
||||
* comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
|
||||
* comprises of SDP Header as defined &struct struct dp_sdp_header in drm_dp_helper.h
|
||||
* and PPS payload defined in &struct drm_dsc_picture_parameter_set.
|
||||
*
|
||||
* @pps_header: Header for PPS as per DP SDP header format
|
||||
* @pps_header: Header for PPS as per DP SDP header format of type
|
||||
* &struct dp_sdp_header
|
||||
* @pps_payload: PPS payload fields as per DSC specification Table 4-1
|
||||
* as represented in &struct drm_dsc_picture_parameter_set
|
||||
*/
|
||||
struct drm_dsc_pps_infoframe {
|
||||
struct dp_sdp_header pps_header;
|
||||
|
|
|
|||
Loading…
Reference in New Issue