powerpc/64s/exception: Remove pointless KVM handler name bifurcation
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190802105709.27696-36-npiggin@gmail.comalistair/sunxi64-5.4-dsi
Nicholas Piggin
Michael Ellerman
parent
1b3599829a
commit
05f97d94dd
|
|
@ -193,12 +193,8 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
|
|||
mtctr reg; \
|
||||
bctr
|
||||
|
||||
.macro INT_KVM_HANDLER vec, hsrr, area, skip
|
||||
.if \hsrr
|
||||
TRAMP_KVM_BEGIN(do_kvm_H\vec\())
|
||||
.else
|
||||
TRAMP_KVM_BEGIN(do_kvm_\vec\())
|
||||
.endif
|
||||
.macro INT_KVM_HANDLER name, vec, hsrr, area, skip
|
||||
TRAMP_KVM_BEGIN(\name\()_kvm)
|
||||
KVM_HANDLER \vec, \hsrr, \area, \skip
|
||||
.endm
|
||||
|
||||
|
|
@ -214,20 +210,10 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
|
|||
#define kvmppc_interrupt kvmppc_interrupt_pr
|
||||
#endif
|
||||
|
||||
.macro KVMTEST hsrr, n
|
||||
.macro KVMTEST name, hsrr, n
|
||||
lbz r10,HSTATE_IN_GUEST(r13)
|
||||
cmpwi r10,0
|
||||
.if \hsrr == EXC_HV_OR_STD
|
||||
BEGIN_FTR_SECTION
|
||||
bne do_kvm_H\n
|
||||
FTR_SECTION_ELSE
|
||||
bne do_kvm_\n
|
||||
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
|
||||
.elseif \hsrr
|
||||
bne do_kvm_H\n
|
||||
.else
|
||||
bne do_kvm_\n
|
||||
.endif
|
||||
bne \name\()_kvm
|
||||
.endm
|
||||
|
||||
.macro KVM_HANDLER vec, hsrr, area, skip
|
||||
|
|
@ -298,9 +284,9 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
|
|||
.endm
|
||||
|
||||
#else
|
||||
.macro KVMTEST hsrr, n
|
||||
.macro KVMTEST name, hsrr, n
|
||||
.endm
|
||||
.macro KVM_HANDLER vec, hsrr, area, skip
|
||||
.macro KVM_HANDLER name, vec, hsrr, area, skip
|
||||
.endm
|
||||
#endif
|
||||
|
||||
|
|
@ -445,7 +431,7 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
|
|||
SAVE_CTR(r10, \area\())
|
||||
mfcr r9
|
||||
.if \kvm
|
||||
KVMTEST \hsrr \vec
|
||||
KVMTEST \name \hsrr \vec
|
||||
.endif
|
||||
.if \bitmask
|
||||
lbz r10,PACAIRQSOFTMASK(r13)
|
||||
|
|
@ -842,7 +828,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
|
|||
*/
|
||||
EXC_REAL_END(system_reset, 0x100, 0x100)
|
||||
EXC_VIRT_NONE(0x4100, 0x100)
|
||||
INT_KVM_HANDLER 0x100, EXC_STD, PACA_EXNMI, 0
|
||||
INT_KVM_HANDLER system_reset 0x100, EXC_STD, PACA_EXNMI, 0
|
||||
|
||||
#ifdef CONFIG_PPC_P7_NAP
|
||||
TRAMP_REAL_BEGIN(system_reset_idle_wake)
|
||||
|
|
@ -936,7 +922,7 @@ TRAMP_REAL_BEGIN(machine_check_fwnmi)
|
|||
INT_HANDLER machine_check, 0x200, early=1, area=PACA_EXMC, dar=1, dsisr=1
|
||||
#endif
|
||||
|
||||
INT_KVM_HANDLER 0x200, EXC_STD, PACA_EXMC, 1
|
||||
INT_KVM_HANDLER machine_check 0x200, EXC_STD, PACA_EXMC, 1
|
||||
|
||||
#define MACHINE_CHECK_HANDLER_WINDUP \
|
||||
/* Clear MSR_RI before setting SRR0 and SRR1. */\
|
||||
|
|
@ -1022,8 +1008,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
|
|||
#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
|
||||
/*
|
||||
* Check if we are coming from guest. If yes, then run the normal
|
||||
* exception handler which will take the do_kvm_200->kvmppc_interrupt
|
||||
* branch to deliver the MC event to guest.
|
||||
* exception handler which will take the
|
||||
* machine_check_kvm->kvmppc_interrupt branch to deliver the MC event
|
||||
* to guest.
|
||||
*/
|
||||
lbz r11,HSTATE_IN_GUEST(r13)
|
||||
cmpwi r11,0 /* Check if coming from guest */
|
||||
|
|
@ -1163,7 +1150,7 @@ EXC_REAL_END(data_access, 0x300, 0x80)
|
|||
EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
|
||||
INT_HANDLER data_access, 0x300, virt=1, dar=1, dsisr=1
|
||||
EXC_VIRT_END(data_access, 0x4300, 0x80)
|
||||
INT_KVM_HANDLER 0x300, EXC_STD, PACA_EXGEN, 1
|
||||
INT_KVM_HANDLER data_access, 0x300, EXC_STD, PACA_EXGEN, 1
|
||||
EXC_COMMON_BEGIN(data_access_common)
|
||||
/*
|
||||
* Here r13 points to the paca, r9 contains the saved CR,
|
||||
|
|
@ -1189,7 +1176,7 @@ EXC_REAL_END(data_access_slb, 0x380, 0x80)
|
|||
EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
|
||||
INT_HANDLER data_access_slb, 0x380, virt=1, area=PACA_EXSLB, dar=1
|
||||
EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
|
||||
INT_KVM_HANDLER 0x380, EXC_STD, PACA_EXSLB, 1
|
||||
INT_KVM_HANDLER data_access_slb, 0x380, EXC_STD, PACA_EXSLB, 1
|
||||
EXC_COMMON_BEGIN(data_access_slb_common)
|
||||
INT_COMMON 0x380, PACA_EXSLB, 1, 1, 0, 1, 0
|
||||
ld r4,_DAR(r1)
|
||||
|
|
@ -1221,7 +1208,7 @@ EXC_REAL_END(instruction_access, 0x400, 0x80)
|
|||
EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
|
||||
INT_HANDLER instruction_access, 0x400, virt=1
|
||||
EXC_VIRT_END(instruction_access, 0x4400, 0x80)
|
||||
INT_KVM_HANDLER 0x400, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER instruction_access, 0x400, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_BEGIN(instruction_access_common)
|
||||
INT_COMMON 0x400, PACA_EXGEN, 1, 1, 1, 2, 2
|
||||
ld r12,_MSR(r1)
|
||||
|
|
@ -1241,7 +1228,7 @@ EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
|
|||
EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
|
||||
INT_HANDLER instruction_access_slb, 0x480, virt=1, area=PACA_EXSLB
|
||||
EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
|
||||
INT_KVM_HANDLER 0x480, EXC_STD, PACA_EXSLB, 0
|
||||
INT_KVM_HANDLER instruction_access_slb, 0x480, EXC_STD, PACA_EXSLB, 0
|
||||
EXC_COMMON_BEGIN(instruction_access_slb_common)
|
||||
INT_COMMON 0x480, PACA_EXSLB, 1, 1, 0, 2, 0
|
||||
ld r4,_DAR(r1)
|
||||
|
|
@ -1272,8 +1259,7 @@ EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
|
|||
EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
|
||||
INT_HANDLER hardware_interrupt, 0x500, virt=1, hsrr=EXC_HV_OR_STD, bitmask=IRQS_DISABLED, kvm=1
|
||||
EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
|
||||
INT_KVM_HANDLER 0x500, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER 0x500, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER hardware_interrupt, 0x500, EXC_HV_OR_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
|
||||
|
||||
|
||||
|
|
@ -1283,7 +1269,7 @@ EXC_REAL_END(alignment, 0x600, 0x100)
|
|||
EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
|
||||
INT_HANDLER alignment, 0x600, virt=1, dar=1, dsisr=1
|
||||
EXC_VIRT_END(alignment, 0x4600, 0x100)
|
||||
INT_KVM_HANDLER 0x600, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER alignment, 0x600, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_BEGIN(alignment_common)
|
||||
INT_COMMON 0x600, PACA_EXGEN, 1, 1, 1, 1, 1
|
||||
bl save_nvgprs
|
||||
|
|
@ -1298,7 +1284,7 @@ EXC_REAL_END(program_check, 0x700, 0x100)
|
|||
EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
|
||||
INT_HANDLER program_check, 0x700, virt=1
|
||||
EXC_VIRT_END(program_check, 0x4700, 0x100)
|
||||
INT_KVM_HANDLER 0x700, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER program_check, 0x700, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_BEGIN(program_check_common)
|
||||
/*
|
||||
* It's possible to receive a TM Bad Thing type program check with
|
||||
|
|
@ -1341,7 +1327,7 @@ EXC_REAL_END(fp_unavailable, 0x800, 0x100)
|
|||
EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
|
||||
INT_HANDLER fp_unavailable, 0x800, virt=1
|
||||
EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
|
||||
INT_KVM_HANDLER 0x800, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER fp_unavailable, 0x800, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_BEGIN(fp_unavailable_common)
|
||||
INT_COMMON 0x800, PACA_EXGEN, 1, 1, 0, 0, 0
|
||||
bne 1f /* if from user, just load it up */
|
||||
|
|
@ -1379,7 +1365,7 @@ EXC_REAL_END(decrementer, 0x900, 0x80)
|
|||
EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
|
||||
INT_HANDLER decrementer, 0x900, virt=1, bitmask=IRQS_DISABLED
|
||||
EXC_VIRT_END(decrementer, 0x4900, 0x80)
|
||||
INT_KVM_HANDLER 0x900, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER decrementer, 0x900, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
|
||||
|
||||
|
||||
|
|
@ -1389,7 +1375,7 @@ EXC_REAL_END(hdecrementer, 0x980, 0x80)
|
|||
EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
|
||||
INT_HANDLER hdecrementer, 0x980, virt=1, hsrr=EXC_HV, kvm=1
|
||||
EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
|
||||
INT_KVM_HANDLER 0x980, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER hdecrementer, 0x980, EXC_HV, PACA_EXGEN, 0
|
||||
EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
|
||||
|
||||
|
||||
|
|
@ -1399,7 +1385,7 @@ EXC_REAL_END(doorbell_super, 0xa00, 0x100)
|
|||
EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
|
||||
INT_HANDLER doorbell_super, 0xa00, virt=1, bitmask=IRQS_DISABLED
|
||||
EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
|
||||
INT_KVM_HANDLER 0xa00, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER doorbell_super, 0xa00, EXC_STD, PACA_EXGEN, 0
|
||||
#ifdef CONFIG_PPC_DOORBELL
|
||||
EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
|
||||
#else
|
||||
|
|
@ -1458,7 +1444,7 @@ EXC_VIRT_NONE(0x4b00, 0x100)
|
|||
GET_PACA(r13)
|
||||
std r10,PACA_EXGEN+EX_R10(r13)
|
||||
INTERRUPT_TO_KERNEL
|
||||
KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */
|
||||
KVMTEST system_call EXC_STD 0xc00 /* uses r10, branch to system_call_kvm */
|
||||
mfctr r9
|
||||
#else
|
||||
mr r9,r13
|
||||
|
|
@ -1524,7 +1510,7 @@ EXC_VIRT_END(system_call, 0x4c00, 0x100)
|
|||
* ctr = orig r13
|
||||
* orig r10 saved in PACA
|
||||
*/
|
||||
TRAMP_KVM_BEGIN(do_kvm_0xc00)
|
||||
TRAMP_KVM_BEGIN(system_call_kvm)
|
||||
/*
|
||||
* Save the PPR (on systems that support it) before changing to
|
||||
* HMT_MEDIUM. That allows the KVM code to save that value into the
|
||||
|
|
@ -1547,7 +1533,7 @@ EXC_REAL_END(single_step, 0xd00, 0x100)
|
|||
EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
|
||||
INT_HANDLER single_step, 0xd00, virt=1
|
||||
EXC_VIRT_END(single_step, 0x4d00, 0x100)
|
||||
INT_KVM_HANDLER 0xd00, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER single_step, 0xd00, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON(single_step_common, 0xd00, single_step_exception)
|
||||
|
||||
|
||||
|
|
@ -1557,7 +1543,7 @@ EXC_REAL_END(h_data_storage, 0xe00, 0x20)
|
|||
EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
|
||||
INT_HANDLER h_data_storage, 0xe00, ool=1, virt=1, hsrr=EXC_HV, dar=1, dsisr=1, kvm=1
|
||||
EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
|
||||
INT_KVM_HANDLER 0xe00, EXC_HV, PACA_EXGEN, 1
|
||||
INT_KVM_HANDLER h_data_storage, 0xe00, EXC_HV, PACA_EXGEN, 1
|
||||
EXC_COMMON_BEGIN(h_data_storage_common)
|
||||
INT_COMMON 0xe00, PACA_EXGEN, 1, 1, 1, 1, 1
|
||||
bl save_nvgprs
|
||||
|
|
@ -1578,7 +1564,7 @@ EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
|
|||
EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
|
||||
INT_HANDLER h_instr_storage, 0xe20, ool=1, virt=1, hsrr=EXC_HV, kvm=1
|
||||
EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
|
||||
INT_KVM_HANDLER 0xe20, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER h_instr_storage, 0xe20, EXC_HV, PACA_EXGEN, 0
|
||||
EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
|
||||
|
||||
|
||||
|
|
@ -1588,7 +1574,7 @@ EXC_REAL_END(emulation_assist, 0xe40, 0x20)
|
|||
EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
|
||||
INT_HANDLER emulation_assist, 0xe40, ool=1, virt=1, hsrr=EXC_HV, kvm=1
|
||||
EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
|
||||
INT_KVM_HANDLER 0xe40, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER emulation_assist, 0xe40, EXC_HV, PACA_EXGEN, 0
|
||||
EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
|
||||
|
||||
|
||||
|
|
@ -1601,7 +1587,7 @@ EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
|
|||
INT_HANDLER hmi_exception, 0xe60, ool=1, early=1, hsrr=EXC_HV, ri=0, kvm=1
|
||||
EXC_REAL_END(hmi_exception, 0xe60, 0x20)
|
||||
EXC_VIRT_NONE(0x4e60, 0x20)
|
||||
INT_KVM_HANDLER 0xe60, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER hmi_exception, 0xe60, EXC_HV, PACA_EXGEN, 0
|
||||
EXC_COMMON_BEGIN(hmi_exception_early_common)
|
||||
mtctr r10 /* Restore ctr */
|
||||
mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
|
||||
|
|
@ -1645,7 +1631,7 @@ EXC_REAL_END(h_doorbell, 0xe80, 0x20)
|
|||
EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
|
||||
INT_HANDLER h_doorbell, 0xe80, ool=1, virt=1, hsrr=EXC_HV, bitmask=IRQS_DISABLED, kvm=1
|
||||
EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
|
||||
INT_KVM_HANDLER 0xe80, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER h_doorbell, 0xe80, EXC_HV, PACA_EXGEN, 0
|
||||
#ifdef CONFIG_PPC_DOORBELL
|
||||
EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
|
||||
#else
|
||||
|
|
@ -1659,7 +1645,7 @@ EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
|
|||
EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
|
||||
INT_HANDLER h_virt_irq, 0xea0, ool=1, virt=1, hsrr=EXC_HV, bitmask=IRQS_DISABLED, kvm=1
|
||||
EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
|
||||
INT_KVM_HANDLER 0xea0, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER h_virt_irq, 0xea0, EXC_HV, PACA_EXGEN, 0
|
||||
EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
|
||||
|
||||
|
||||
|
|
@ -1675,7 +1661,7 @@ EXC_REAL_END(performance_monitor, 0xf00, 0x20)
|
|||
EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
|
||||
INT_HANDLER performance_monitor, 0xf00, ool=1, virt=1, bitmask=IRQS_PMI_DISABLED
|
||||
EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
|
||||
INT_KVM_HANDLER 0xf00, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER performance_monitor, 0xf00, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
|
||||
|
||||
|
||||
|
|
@ -1685,7 +1671,7 @@ EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
|
|||
EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
|
||||
INT_HANDLER altivec_unavailable, 0xf20, ool=1, virt=1
|
||||
EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
|
||||
INT_KVM_HANDLER 0xf20, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER altivec_unavailable, 0xf20, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_BEGIN(altivec_unavailable_common)
|
||||
INT_COMMON 0xf20, PACA_EXGEN, 1, 1, 0, 0, 0
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
|
|
@ -1726,7 +1712,7 @@ EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
|
|||
EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
|
||||
INT_HANDLER vsx_unavailable, 0xf40, ool=1, virt=1
|
||||
EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
|
||||
INT_KVM_HANDLER 0xf40, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER vsx_unavailable, 0xf40, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON_BEGIN(vsx_unavailable_common)
|
||||
INT_COMMON 0xf40, PACA_EXGEN, 1, 1, 0, 0, 0
|
||||
#ifdef CONFIG_VSX
|
||||
|
|
@ -1766,7 +1752,7 @@ EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
|
|||
EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
|
||||
INT_HANDLER facility_unavailable, 0xf60, ool=1, virt=1
|
||||
EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
|
||||
INT_KVM_HANDLER 0xf60, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER facility_unavailable, 0xf60, EXC_STD, PACA_EXGEN, 0
|
||||
EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
|
||||
|
||||
|
||||
|
|
@ -1776,7 +1762,7 @@ EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
|
|||
EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
|
||||
INT_HANDLER h_facility_unavailable, 0xf80, ool=1, virt=1, hsrr=EXC_HV, kvm=1
|
||||
EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
|
||||
INT_KVM_HANDLER 0xf80, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER h_facility_unavailable, 0xf80, EXC_HV, PACA_EXGEN, 0
|
||||
EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
|
||||
|
||||
|
||||
|
|
@ -1797,7 +1783,7 @@ EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
|
|||
INT_HANDLER cbe_system_error, 0x1200, ool=1, hsrr=EXC_HV, kvm=1
|
||||
EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
|
||||
EXC_VIRT_NONE(0x5200, 0x100)
|
||||
INT_KVM_HANDLER 0x1200, EXC_HV, PACA_EXGEN, 1
|
||||
INT_KVM_HANDLER cbe_system_error, 0x1200, EXC_HV, PACA_EXGEN, 1
|
||||
EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
|
||||
#else /* CONFIG_CBE_RAS */
|
||||
EXC_REAL_NONE(0x1200, 0x100)
|
||||
|
|
@ -1811,7 +1797,7 @@ EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
|
|||
EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
|
||||
INT_HANDLER instruction_breakpoint, 0x1300, virt=1
|
||||
EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
|
||||
INT_KVM_HANDLER 0x1300, EXC_STD, PACA_EXGEN, 1
|
||||
INT_KVM_HANDLER instruction_breakpoint, 0x1300, EXC_STD, PACA_EXGEN, 1
|
||||
EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
|
||||
|
||||
|
||||
|
|
@ -1825,7 +1811,7 @@ EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
|
|||
andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
|
||||
bne+ denorm_assist
|
||||
#endif
|
||||
KVMTEST EXC_HV 0x1500
|
||||
KVMTEST denorm_exception_hv, EXC_HV 0x1500
|
||||
INT_SAVE_SRR_AND_JUMP denorm_common, EXC_HV, 1
|
||||
EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
|
||||
|
||||
|
|
@ -1841,7 +1827,7 @@ EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
|
|||
EXC_VIRT_NONE(0x5500, 0x100)
|
||||
#endif
|
||||
|
||||
INT_KVM_HANDLER 0x1500, EXC_HV, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER denorm_exception_hv, 0x1500, EXC_HV, PACA_EXGEN, 0
|
||||
|
||||
#ifdef CONFIG_PPC_DENORMALISATION
|
||||
TRAMP_REAL_BEGIN(denorm_assist)
|
||||
|
|
@ -1920,7 +1906,7 @@ EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
|
|||
INT_HANDLER cbe_maintenance, 0x1600, ool=1, hsrr=EXC_HV, kvm=1
|
||||
EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
|
||||
EXC_VIRT_NONE(0x5600, 0x100)
|
||||
INT_KVM_HANDLER 0x1600, EXC_HV, PACA_EXGEN, 1
|
||||
INT_KVM_HANDLER cbe_maintenance, 0x1600, EXC_HV, PACA_EXGEN, 1
|
||||
EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
|
||||
#else /* CONFIG_CBE_RAS */
|
||||
EXC_REAL_NONE(0x1600, 0x100)
|
||||
|
|
@ -1934,7 +1920,7 @@ EXC_REAL_END(altivec_assist, 0x1700, 0x100)
|
|||
EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
|
||||
INT_HANDLER altivec_assist, 0x1700, virt=1
|
||||
EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
|
||||
INT_KVM_HANDLER 0x1700, EXC_STD, PACA_EXGEN, 0
|
||||
INT_KVM_HANDLER altivec_assist, 0x1700, EXC_STD, PACA_EXGEN, 0
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
|
||||
#else
|
||||
|
|
@ -1947,7 +1933,7 @@ EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
|
|||
INT_HANDLER cbe_thermal, 0x1800, ool=1, hsrr=EXC_HV, kvm=1
|
||||
EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
|
||||
EXC_VIRT_NONE(0x5800, 0x100)
|
||||
INT_KVM_HANDLER 0x1800, EXC_HV, PACA_EXGEN, 1
|
||||
INT_KVM_HANDLER cbe_thermal, 0x1800, EXC_HV, PACA_EXGEN, 1
|
||||
EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
|
||||
#else /* CONFIG_CBE_RAS */
|
||||
EXC_REAL_NONE(0x1800, 0x100)
|
||||
|
|
|
|||
Loading…
Reference in New Issue