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Staging: dt3155: coding cleanups for dt3155_io.h

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This fixes up some coding style issues in the dt3155_io.h file

Cc: Scott Smedley <ss@aao.gov.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman 2010-02-09 12:38:13 -08:00
parent f721ad7a9c
commit 062d164719
1 changed files with 209 additions and 248 deletions
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99
drivers/staging/dt3155/dt3155_io.h
View file

@ -70,13 +70,9 @@ MA 02111-1307 USA
/******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/
/**********************************
* fifo_trigger_tag
*/
typedef union fifo_trigger_tag {
u_long reg;
struct
{
struct {
u_long PACKED:6;
u_long :9;
u_long PLANER:7;
@ -84,13 +80,9 @@ typedef union fifo_trigger_tag {
} fld;
} FIFO_TRIGGER_R;
/**********************************
* xfer_mode_tag
*/
typedef union xfer_mode_tag {
u_long reg;
struct
{
struct {
u_long :2;
u_long FIELD_TOGGLE:1;
u_long :5;
@ -99,13 +91,9 @@ typedef union xfer_mode_tag {
} fld;
} XFER_MODE_R;
/**********************************
* csr1_tag
*/
typedef union csr1_tag {
u_long reg;
struct
{
struct {
u_long CAP_CONT_EVE:1;
u_long CAP_CONT_ODD:1;
u_long CAP_SNGL_EVE:1;
@ -124,25 +112,17 @@ typedef union csr1_tag {
} fld;
} CSR1_R;
/**********************************
* retry_wait_cnt_tag
*/
typedef union retry_wait_cnt_tag {
u_long reg;
struct
{
struct {
u_long RTRY_WAIT_CNT:8;
u_long :24;
} fld;
} RETRY_WAIT_CNT_R;
/**********************************
* int_csr_tag
*/
typedef union int_csr_tag {
u_long reg;
struct
{
struct {
u_long FLD_END_EVE :1;
u_long FLD_END_ODD :1;
u_long FLD_START :1;
@ -154,13 +134,9 @@ typedef union int_csr_tag {
} fld;
} INT_CSR_R;
/**********************************
* mask_length_tag
*/
typedef union mask_length_tag {
u_long reg;
struct
{
struct {
u_long MASK_LEN_EVE:5;
u_long :11;
u_long MASK_LEN_ODD:5;
@ -168,13 +144,9 @@ typedef union mask_length_tag {
} fld;
} MASK_LENGTH_R;
/**********************************
* fifo_flag_cnt_tag
*/
typedef union fifo_flag_cnt_tag {
u_long reg;
struct
{
struct {
u_long AF_COUNT:7;
u_long :9;
u_long AE_COUNT:7;
@ -182,13 +154,9 @@ typedef union fifo_flag_cnt_tag {
} fld;
} FIFO_FLAG_CNT_R;
/**********************************
* iic_clk_dur
*/
typedef union iic_clk_dur {
u_long reg;
struct
{
struct {
u_long PHASE_1:8;
u_long PHASE_2:8;
u_long PHASE_3:8;
@ -196,13 +164,9 @@ typedef union iic_clk_dur {
} fld;
} IIC_CLK_DUR_R;
/**********************************
* iic_csr1_tag
*/
typedef union iic_csr1_tag {
u_long reg;
struct
{
struct {
u_long AUTO_EN :1;
u_long BYPASS :1;
u_long SDA_OUT :1;
@ -223,8 +187,7 @@ typedef union iic_csr1_tag {
*/
typedef union iic_csr2_tag {
u_long reg;
struct
{
struct {
u_long DIR_WR_DATA :8;
u_long DIR_SUB_ADDR:8;
u_long DIR_RD :1;
@ -236,7 +199,7 @@ typedef union iic_csr2_tag {
/* use for both EVEN and ODD DMA UPPER LIMITS */
/**********************************
/*
* dma_upper_lmt_tag
*/
typedef union dma_upper_lmt_tag {
@ -248,10 +211,9 @@ typedef union dma_upper_lmt_tag {
} DMA_UPPER_LMT_R;
/***************************************
* Global declarations of local copies
* of boards' 32 bit registers
***************************************/
/*
* Global declarations of local copies of boards' 32 bit registers
*/
extern u_long even_dma_start_r; /* bit 0 should always be 0 */
extern u_long odd_dma_start_r; /* .. */
extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */
@ -279,7 +241,6 @@ extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r;
/***************** 8 bit I2C register globals ***********/
#define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/
#define EVEN_CSR 0x011
#define ODD_CSR 0x012
@ -324,8 +285,7 @@ typedef union i2c_even_csr_tag {
typedef union i2c_odd_csr_tag {
u_char reg;
struct
{
struct {
u_char DONE_ODD:1;
u_char SNGL_ODD:1;
u_char ERROR_ODD:1;
@ -335,8 +295,7 @@ typedef union i2c_odd_csr_tag {
typedef union i2c_config_tag {
u_char reg;
struct
{
struct {
u_char ACQ_MODE:2;
u_char EXT_TRIG_EN:1;
u_char EXT_TRIG_POL:1;
@ -348,25 +307,27 @@ typedef union i2c_config_tag {
} I2C_CONFIG;
typedef union i2c_ad_cmd_tag { /* bits can have 3 different meanings
depending on value of AD_ADDR */
typedef union i2c_ad_cmd_tag {
/* bits can have 3 different meanings depending on value of AD_ADDR */
u_char reg;
struct
{
/* Bt252 Command Register if AD_ADDR = 00h */
struct {
u_char :2;
u_char SYNC_LVL_SEL:2;
u_char SYNC_CNL_SEL:2;
u_char DIGITIZE_CNL_SEL1:2;
} bt252_command; /* Bt252 Command Register */
struct /* if AD_ADDR = 00h */
{
} bt252_command;
/* Bt252 IOUT0 register if AD_ADDR = 01h */
struct {
u_char IOUT_DATA:8;
} bt252_iout0; /* Bt252 IOUT0 register */
struct /* if AD_ADDR = 01h */
{
} bt252_iout0;
/* BT252 IOUT1 register if AD_ADDR = 02h */
struct {
u_char IOUT_DATA:8;
} bt252_iout1; /* BT252 IOUT1 register */
} I2C_AD_CMD; /* if AD_ADDR = 02h */
} bt252_iout1;
} I2C_AD_CMD;
/***** Global declarations of local copies of boards' 8 bit I2C registers ***/