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x86: unmask CPUID levels on Intel CPUs 

Impact: Fixes crashes with misconfigured BIOSes on XSAVE hardware

Avuton Olrich reported early boot crashes with v2.6.28 and
bisected it down to dc1e35c6e9
("x86, xsave: enable xsave/xrstor on cpus with xsave support").

If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
make all CPUID information available.  This is required for some
features to work, in particular XSAVE.

Reported-and-bisected-by: Avuton Olrich <avuton@gmail.com>
Tested-by: Avuton Olrich <avuton@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
hifive-unleashed-5.1
H. Peter Anvin 2009-01-21 15:04:32 -08:00 committed by Ingo Molnar
parent bdf21a49ba
commit 066941bd4e
1 changed files with 10 additions and 0 deletions
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10
arch/x86/kernel/cpu/intel.c
View File

@ -29,6 +29,16 @@
static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
u64 misc_enable;
/* Unmask CPUID levels if masked */
if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
(misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
c->cpuid_level = cpuid_eax(0);
}
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);