drm/radeon: add radeon_asic struct for CIK (v12)
v2: fix up for latest reset changes v3: use CP for pt updates for now v4: update for 2 level PTs v5: update for ib_parse removal v6: vm_flush api change v7: rebase v8: fix gfx ring function pointers v9: fix vm_set_page function params v10: update for compute changes v11: cleanup for release v12: update rptr/wptr callbacks Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
0aafd3133f
commit
0672e27bea
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@ -2055,6 +2055,316 @@ static struct radeon_asic si_asic = {
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},
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},
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};
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};
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static struct radeon_asic ci_asic = {
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.init = &cik_init,
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.fini = &cik_fini,
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.suspend = &cik_suspend,
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.resume = &cik_resume,
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.asic_reset = &cik_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
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.gart = {
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.tlb_flush = &cik_pcie_gart_tlb_flush,
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.set_page = &rs600_gart_set_page,
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},
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.vm = {
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.init = &cik_vm_init,
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.fini = &cik_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.set_page = &cik_vm_set_page,
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},
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.ring = {
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[RADEON_RING_TYPE_GFX_INDEX] = {
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.ib_execute = &cik_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_fence_gfx_ring_emit,
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.emit_semaphore = &cik_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_ring_test,
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.ib_test = &cik_ib_test,
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.is_lockup = &cik_gfx_is_lockup,
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.vm_flush = &cik_vm_flush,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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},
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[CAYMAN_RING_TYPE_CP1_INDEX] = {
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.ib_execute = &cik_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_fence_compute_ring_emit,
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.emit_semaphore = &cik_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_ring_test,
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.ib_test = &cik_ib_test,
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.is_lockup = &cik_gfx_is_lockup,
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.vm_flush = &cik_vm_flush,
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.get_rptr = &cik_compute_ring_get_rptr,
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.get_wptr = &cik_compute_ring_get_wptr,
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.set_wptr = &cik_compute_ring_set_wptr,
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},
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[CAYMAN_RING_TYPE_CP2_INDEX] = {
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.ib_execute = &cik_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_fence_compute_ring_emit,
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.emit_semaphore = &cik_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_ring_test,
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.ib_test = &cik_ib_test,
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.is_lockup = &cik_gfx_is_lockup,
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.vm_flush = &cik_vm_flush,
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.get_rptr = &cik_compute_ring_get_rptr,
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.get_wptr = &cik_compute_ring_get_wptr,
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.set_wptr = &cik_compute_ring_set_wptr,
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},
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[R600_RING_TYPE_DMA_INDEX] = {
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.ib_execute = &cik_sdma_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_sdma_fence_ring_emit,
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.emit_semaphore = &cik_sdma_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_sdma_ring_test,
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.ib_test = &cik_sdma_ib_test,
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.is_lockup = &cik_sdma_is_lockup,
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.vm_flush = &cik_dma_vm_flush,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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},
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[CAYMAN_RING_TYPE_DMA1_INDEX] = {
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.ib_execute = &cik_sdma_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_sdma_fence_ring_emit,
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.emit_semaphore = &cik_sdma_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_sdma_ring_test,
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.ib_test = &cik_sdma_ib_test,
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.is_lockup = &cik_sdma_is_lockup,
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.vm_flush = &cik_dma_vm_flush,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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},
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[R600_RING_TYPE_UVD_INDEX] = {
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.ib_execute = &r600_uvd_ib_execute,
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.emit_fence = &r600_uvd_fence_emit,
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.emit_semaphore = &cayman_uvd_semaphore_emit,
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.cs_parse = &radeon_uvd_cs_parse,
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.ring_test = &r600_uvd_ring_test,
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.ib_test = &r600_uvd_ib_test,
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.is_lockup = &radeon_ring_test_lockup,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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}
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},
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.irq = {
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.set = &cik_irq_set,
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.process = &cik_irq_process,
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},
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.display = {
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.bandwidth_update = &dce8_bandwidth_update,
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.get_vblank_counter = &evergreen_get_vblank_counter,
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.wait_for_vblank = &dce4_wait_for_vblank,
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},
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.copy = {
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.blit = NULL,
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.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.dma = &cik_copy_dma,
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.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
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.copy = &cik_copy_dma,
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.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
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},
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.surface = {
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.set_reg = r600_set_surface_reg,
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.clear_reg = r600_clear_surface_reg,
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},
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.hpd = {
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.init = &evergreen_hpd_init,
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.fini = &evergreen_hpd_fini,
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.sense = &evergreen_hpd_sense,
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.set_polarity = &evergreen_hpd_set_polarity,
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},
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.pm = {
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.misc = &evergreen_pm_misc,
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.prepare = &evergreen_pm_prepare,
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.finish = &evergreen_pm_finish,
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.init_profile = &sumo_pm_init_profile,
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.get_dynpm_state = &r600_pm_get_dynpm_state,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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.set_memory_clock = &radeon_atom_set_memory_clock,
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
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.set_clock_gating = NULL,
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.set_uvd_clocks = &cik_set_uvd_clocks,
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},
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.pflip = {
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.pre_page_flip = &evergreen_pre_page_flip,
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.page_flip = &evergreen_page_flip,
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.post_page_flip = &evergreen_post_page_flip,
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},
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};
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static struct radeon_asic kv_asic = {
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.init = &cik_init,
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.fini = &cik_fini,
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.suspend = &cik_suspend,
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.resume = &cik_resume,
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.asic_reset = &cik_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
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.gart = {
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.tlb_flush = &cik_pcie_gart_tlb_flush,
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.set_page = &rs600_gart_set_page,
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},
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.vm = {
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.init = &cik_vm_init,
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.fini = &cik_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.set_page = &cik_vm_set_page,
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},
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.ring = {
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[RADEON_RING_TYPE_GFX_INDEX] = {
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.ib_execute = &cik_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_fence_gfx_ring_emit,
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.emit_semaphore = &cik_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_ring_test,
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.ib_test = &cik_ib_test,
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.is_lockup = &cik_gfx_is_lockup,
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.vm_flush = &cik_vm_flush,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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},
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[CAYMAN_RING_TYPE_CP1_INDEX] = {
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.ib_execute = &cik_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_fence_compute_ring_emit,
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.emit_semaphore = &cik_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_ring_test,
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.ib_test = &cik_ib_test,
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.is_lockup = &cik_gfx_is_lockup,
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.vm_flush = &cik_vm_flush,
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.get_rptr = &cik_compute_ring_get_rptr,
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.get_wptr = &cik_compute_ring_get_wptr,
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.set_wptr = &cik_compute_ring_set_wptr,
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},
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[CAYMAN_RING_TYPE_CP2_INDEX] = {
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.ib_execute = &cik_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_fence_compute_ring_emit,
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.emit_semaphore = &cik_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_ring_test,
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.ib_test = &cik_ib_test,
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.is_lockup = &cik_gfx_is_lockup,
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.vm_flush = &cik_vm_flush,
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.get_rptr = &cik_compute_ring_get_rptr,
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.get_wptr = &cik_compute_ring_get_wptr,
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.set_wptr = &cik_compute_ring_set_wptr,
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},
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[R600_RING_TYPE_DMA_INDEX] = {
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.ib_execute = &cik_sdma_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_sdma_fence_ring_emit,
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.emit_semaphore = &cik_sdma_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_sdma_ring_test,
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.ib_test = &cik_sdma_ib_test,
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.is_lockup = &cik_sdma_is_lockup,
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.vm_flush = &cik_dma_vm_flush,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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},
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[CAYMAN_RING_TYPE_DMA1_INDEX] = {
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.ib_execute = &cik_sdma_ring_ib_execute,
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.ib_parse = &cik_ib_parse,
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.emit_fence = &cik_sdma_fence_ring_emit,
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.emit_semaphore = &cik_sdma_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &cik_sdma_ring_test,
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.ib_test = &cik_sdma_ib_test,
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.is_lockup = &cik_sdma_is_lockup,
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.vm_flush = &cik_dma_vm_flush,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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},
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[R600_RING_TYPE_UVD_INDEX] = {
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.ib_execute = &r600_uvd_ib_execute,
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.emit_fence = &r600_uvd_fence_emit,
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.emit_semaphore = &cayman_uvd_semaphore_emit,
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.cs_parse = &radeon_uvd_cs_parse,
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.ring_test = &r600_uvd_ring_test,
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.ib_test = &r600_uvd_ib_test,
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.is_lockup = &radeon_ring_test_lockup,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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}
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},
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.irq = {
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.set = &cik_irq_set,
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.process = &cik_irq_process,
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},
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.display = {
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.bandwidth_update = &dce8_bandwidth_update,
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.get_vblank_counter = &evergreen_get_vblank_counter,
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.wait_for_vblank = &dce4_wait_for_vblank,
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},
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.copy = {
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.blit = NULL,
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.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.dma = &cik_copy_dma,
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.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
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.copy = &cik_copy_dma,
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.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
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},
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.surface = {
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.set_reg = r600_set_surface_reg,
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.clear_reg = r600_clear_surface_reg,
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},
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.hpd = {
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.init = &evergreen_hpd_init,
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.fini = &evergreen_hpd_fini,
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.sense = &evergreen_hpd_sense,
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.set_polarity = &evergreen_hpd_set_polarity,
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},
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.pm = {
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.misc = &evergreen_pm_misc,
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.prepare = &evergreen_pm_prepare,
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.finish = &evergreen_pm_finish,
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.init_profile = &sumo_pm_init_profile,
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.get_dynpm_state = &r600_pm_get_dynpm_state,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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.set_memory_clock = &radeon_atom_set_memory_clock,
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
|
||||||
|
.set_clock_gating = NULL,
|
||||||
|
.set_uvd_clocks = &cik_set_uvd_clocks,
|
||||||
|
},
|
||||||
|
.pflip = {
|
||||||
|
.pre_page_flip = &evergreen_pre_page_flip,
|
||||||
|
.page_flip = &evergreen_page_flip,
|
||||||
|
.post_page_flip = &evergreen_post_page_flip,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* radeon_asic_init - register asic specific callbacks
|
* radeon_asic_init - register asic specific callbacks
|
||||||
*
|
*
|
||||||
|
@ -2218,6 +2528,19 @@ int radeon_asic_init(struct radeon_device *rdev)
|
||||||
else
|
else
|
||||||
rdev->has_uvd = true;
|
rdev->has_uvd = true;
|
||||||
break;
|
break;
|
||||||
|
case CHIP_BONAIRE:
|
||||||
|
rdev->asic = &ci_asic;
|
||||||
|
rdev->num_crtc = 6;
|
||||||
|
break;
|
||||||
|
case CHIP_KAVERI:
|
||||||
|
case CHIP_KABINI:
|
||||||
|
rdev->asic = &kv_asic;
|
||||||
|
/* set num crtcs */
|
||||||
|
if (rdev->family == CHIP_KAVERI)
|
||||||
|
rdev->num_crtc = 4;
|
||||||
|
else
|
||||||
|
rdev->num_crtc = 2;
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
/* FIXME: not supported yet */
|
/* FIXME: not supported yet */
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
|
@ -559,6 +559,9 @@ u32 si_get_xclk(struct radeon_device *rdev);
|
||||||
uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
|
uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
|
||||||
int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
|
int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
|
||||||
|
|
||||||
|
/* DCE8 - CIK */
|
||||||
|
void dce8_bandwidth_update(struct radeon_device *rdev);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* cik
|
* cik
|
||||||
*/
|
*/
|
||||||
|
@ -568,5 +571,55 @@ uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
|
||||||
void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
|
void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
|
||||||
int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
|
int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
|
||||||
int cik_uvd_resume(struct radeon_device *rdev);
|
int cik_uvd_resume(struct radeon_device *rdev);
|
||||||
|
void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
|
||||||
|
struct radeon_fence *fence);
|
||||||
|
void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
|
||||||
|
struct radeon_ring *ring,
|
||||||
|
struct radeon_semaphore *semaphore,
|
||||||
|
bool emit_wait);
|
||||||
|
void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||||
|
int cik_copy_dma(struct radeon_device *rdev,
|
||||||
|
uint64_t src_offset, uint64_t dst_offset,
|
||||||
|
unsigned num_gpu_pages,
|
||||||
|
struct radeon_fence **fence);
|
||||||
|
int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||||
|
int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||||
|
bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||||
|
void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
|
||||||
|
struct radeon_fence *fence);
|
||||||
|
void cik_fence_compute_ring_emit(struct radeon_device *rdev,
|
||||||
|
struct radeon_fence *fence);
|
||||||
|
void cik_semaphore_ring_emit(struct radeon_device *rdev,
|
||||||
|
struct radeon_ring *cp,
|
||||||
|
struct radeon_semaphore *semaphore,
|
||||||
|
bool emit_wait);
|
||||||
|
void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
||||||
|
int cik_init(struct radeon_device *rdev);
|
||||||
|
void cik_fini(struct radeon_device *rdev);
|
||||||
|
int cik_suspend(struct radeon_device *rdev);
|
||||||
|
int cik_resume(struct radeon_device *rdev);
|
||||||
|
bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||||
|
int cik_asic_reset(struct radeon_device *rdev);
|
||||||
|
void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||||
|
int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||||
|
int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||||
|
int cik_irq_set(struct radeon_device *rdev);
|
||||||
|
int cik_irq_process(struct radeon_device *rdev);
|
||||||
|
int cik_vm_init(struct radeon_device *rdev);
|
||||||
|
void cik_vm_fini(struct radeon_device *rdev);
|
||||||
|
void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
|
||||||
|
void cik_vm_set_page(struct radeon_device *rdev,
|
||||||
|
struct radeon_ib *ib,
|
||||||
|
uint64_t pe,
|
||||||
|
uint64_t addr, unsigned count,
|
||||||
|
uint32_t incr, uint32_t flags);
|
||||||
|
void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
|
||||||
|
int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||||
|
u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
|
||||||
|
struct radeon_ring *ring);
|
||||||
|
u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
|
||||||
|
struct radeon_ring *ring);
|
||||||
|
void cik_compute_ring_set_wptr(struct radeon_device *rdev,
|
||||||
|
struct radeon_ring *ring);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue