drm/i915/cmdparser: Add the TIMESTAMP register for the other engines
Since I have been using the BCS_TIMESTAMP to measure latency of execution upon the blitter ring, allow regular userspace to also read from that register. They are already allowed RCS_TIMESTAMP! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20160818161718.27187-32-chris@chris-wilson.co.uk
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@ -458,6 +458,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
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REG32(GEN7_GPGPU_DISPATCHDIMX),
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REG32(GEN7_GPGPU_DISPATCHDIMX),
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REG32(GEN7_GPGPU_DISPATCHDIMY),
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REG32(GEN7_GPGPU_DISPATCHDIMY),
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REG32(GEN7_GPGPU_DISPATCHDIMZ),
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REG32(GEN7_GPGPU_DISPATCHDIMZ),
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REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
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REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
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REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
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REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
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REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
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REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
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REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
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@ -473,6 +474,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
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REG32(GEN7_L3SQCREG1),
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REG32(GEN7_L3SQCREG1),
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REG32(GEN7_L3CNTLREG2),
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REG32(GEN7_L3CNTLREG2),
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REG32(GEN7_L3CNTLREG3),
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REG32(GEN7_L3CNTLREG3),
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REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
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};
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};
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static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
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static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
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@ -502,7 +504,10 @@ static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
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};
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};
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static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
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static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
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REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
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REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
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REG32(BCS_SWCTRL),
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REG32(BCS_SWCTRL),
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REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
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};
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};
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static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
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static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
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