drm/radeon/kms: detect sideport memory on IGP chips
This detects if the sideport memory is enabled and if it is VRAM is evicted on suspend/resume. This should fix s/r issues on some IGPs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -726,6 +726,10 @@ int r600_mc_init(struct radeon_device *rdev)
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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if (rdev->flags & RADEON_IS_IGP)
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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return 0;
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}
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@ -319,10 +319,12 @@ struct radeon_mc {
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u64 real_vram_size;
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int vram_mtrr;
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bool vram_is_ddr;
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bool igp_sideport_enabled;
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};
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int radeon_mc_setup(struct radeon_device *rdev);
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bool radeon_combios_sideport_present(struct radeon_device *rdev);
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bool radeon_atombios_sideport_present(struct radeon_device *rdev);
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/*
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* GPU scratch registers structures, functions & helpers
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@ -938,6 +938,43 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
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return false;
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}
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union igp_info {
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struct _ATOM_INTEGRATED_SYSTEM_INFO info;
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struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
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};
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bool radeon_atombios_sideport_present(struct radeon_device *rdev)
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{
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struct radeon_mode_info *mode_info = &rdev->mode_info;
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int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
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union igp_info *igp_info;
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u8 frev, crev;
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u16 data_offset;
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atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
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&crev, &data_offset);
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igp_info = (union igp_info *)(mode_info->atom_context->bios +
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data_offset);
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if (igp_info) {
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switch (crev) {
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case 1:
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if (igp_info->info.ucMemoryType & 0xf0)
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return true;
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break;
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case 2:
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if (igp_info->info_2.ucMemoryType & 0x0f)
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return true;
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break;
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default:
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DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
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break;
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}
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}
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return false;
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}
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bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
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struct radeon_encoder_int_tmds *tmds)
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{
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@ -595,6 +595,20 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
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return false;
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}
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bool radeon_combios_sideport_present(struct radeon_device *rdev)
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{
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struct drm_device *dev = rdev->ddev;
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u16 igp_info;
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igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
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if (igp_info) {
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if (RBIOS16(igp_info + 0x4))
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return true;
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}
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return false;
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}
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static const uint32_t default_primarydac_adj[CHIP_LAST] = {
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0x00000808, /* r100 */
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0x00000808, /* rv100 */
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@ -221,8 +221,9 @@ int radeon_bo_unpin(struct radeon_bo *bo)
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int radeon_bo_evict_vram(struct radeon_device *rdev)
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{
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if (rdev->flags & RADEON_IS_IGP) {
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/* Useless to evict on IGP chips */
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return 0;
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if (rdev->mc.igp_sideport_enabled == false)
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/* Useless to evict on IGP chips */
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return 0;
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}
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return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
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}
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@ -356,6 +356,7 @@ static int rs400_mc_init(struct radeon_device *rdev)
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rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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r = radeon_mc_setup(rdev);
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rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
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if (r)
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return r;
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return 0;
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@ -56,6 +56,7 @@ int rs600_mc_init(struct radeon_device *rdev)
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rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
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rdev->mc.gtt_location = 0xffffffffUL;
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r = radeon_mc_setup(rdev);
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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if (r)
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return r;
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return 0;
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@ -172,6 +172,7 @@ static int rs690_mc_init(struct radeon_device *rdev)
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rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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r = radeon_mc_setup(rdev);
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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if (r)
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return r;
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return 0;
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