[ARM] 4262/1: OMAP: clocksource and clockevent support
Update OMAP1 to enable support for hrtimers and dynticks by using new clocksource and clockevent infrastructure. Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Kevin Hilman
Russell King
parent
89df127246
commit
075192ae80
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@ -370,6 +370,7 @@ config ARCH_LH7A40X
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config ARCH_OMAP
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bool "TI OMAP"
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select GENERIC_GPIO
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select GENERIC_TIME
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help
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Support for TI's OMAP platform (OMAP1 and OMAP2).
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@ -39,6 +39,10 @@
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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@ -48,13 +52,7 @@
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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struct sys_timer omap_timer;
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/*
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* ---------------------------------------------------------------------------
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* MPU timer
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* ---------------------------------------------------------------------------
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*/
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#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
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#define OMAP_MPU_TIMER_OFFSET 0x100
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@ -88,21 +86,6 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
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return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
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}
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/*
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* MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
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* will break. On P2, the timer count rate is 6.5 MHz after programming PTV
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* with 0. This divides the 13MHz input by 2, and is undocumented.
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*/
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#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
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/* REVISIT: This ifdef construct should be replaced by a query to clock
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* framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
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*/
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#define MPU_TICKS_PER_SEC (13000000 / 2)
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#else
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#define MPU_TICKS_PER_SEC (12000000 / 2)
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#endif
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#define MPU_TIMER_TICK_PERIOD ((MPU_TICKS_PER_SEC / HZ) - 1)
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typedef struct {
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u32 cntl; /* CNTL_TIMER, R/W */
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@ -120,98 +103,164 @@ static inline unsigned long omap_mpu_timer_read(int nr)
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return timer->read_tim;
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}
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static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
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static inline void omap_mpu_set_autoreset(int nr)
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{
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volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
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timer->cntl = timer->cntl | MPU_TIMER_AR;
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}
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static inline void omap_mpu_remove_autoreset(int nr)
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{
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volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
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timer->cntl = timer->cntl & ~MPU_TIMER_AR;
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}
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static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
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int autoreset)
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{
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volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
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unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);
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if (autoreset) timerflags |= MPU_TIMER_AR;
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timer->cntl = MPU_TIMER_CLOCK_ENABLE;
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udelay(1);
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timer->load_tim = load_val;
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udelay(1);
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timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
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}
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unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
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{
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unsigned long long nsec;
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nsec = cycles_2_ns((unsigned long long)nr_ticks);
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return (unsigned long)nsec / 1000;
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timer->cntl = timerflags;
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}
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/*
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* Last processed system timer interrupt
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* ---------------------------------------------------------------------------
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* MPU timer 1 ... count down to zero, interrupt, reload
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* ---------------------------------------------------------------------------
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*/
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static unsigned long omap_mpu_timer_last = 0;
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/*
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* Returns elapsed usecs since last system timer interrupt
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*/
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static unsigned long omap_mpu_timer_gettimeoffset(void)
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static int omap_mpu_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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unsigned long now = 0 - omap_mpu_timer_read(0);
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unsigned long elapsed = now - omap_mpu_timer_last;
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return omap_mpu_timer_ticks_to_usecs(elapsed);
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omap_mpu_timer_start(0, cycles, 0);
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return 0;
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}
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/*
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* Elapsed time between interrupts is calculated using timer0.
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* Latency during the interrupt is calculated using timer1.
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* Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
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*/
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static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id)
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static void omap_mpu_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long now, latency;
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write_seqlock(&xtime_lock);
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now = 0 - omap_mpu_timer_read(0);
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latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
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omap_mpu_timer_last = now - latency;
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timer_tick();
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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omap_mpu_set_autoreset(0);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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omap_mpu_remove_autoreset(0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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break;
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}
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}
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static struct irqaction omap_mpu_timer_irq = {
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.name = "mpu timer",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = omap_mpu_timer_interrupt,
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static struct clock_event_device clockevent_mpu_timer1 = {
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.name = "mpu_timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC, CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_next_event = omap_mpu_set_next_event,
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.set_mode = omap_mpu_set_mode,
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};
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static unsigned long omap_mpu_timer1_overflows;
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static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
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{
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omap_mpu_timer1_overflows++;
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struct clock_event_device *evt = &clockevent_mpu_timer1;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction omap_mpu_timer1_irq = {
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.name = "mpu timer1 overflow",
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.flags = IRQF_DISABLED,
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.name = "mpu_timer1",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = omap_mpu_timer1_interrupt,
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};
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static __init void omap_init_mpu_timer(void)
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static __init void omap_init_mpu_timer(unsigned long rate)
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{
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set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
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omap_timer.offset = omap_mpu_timer_gettimeoffset;
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set_cyc2ns_scale(rate / 1000);
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setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
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setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
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omap_mpu_timer_start(0, 0xffffffff);
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omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
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omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
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clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
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clockevent_mpu_timer1.shift);
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clockevent_mpu_timer1.max_delta_ns =
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clockevent_delta2ns(-1, &clockevent_mpu_timer1);
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clockevent_mpu_timer1.min_delta_ns =
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clockevent_delta2ns(1, &clockevent_mpu_timer1);
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clockevent_mpu_timer1.cpumask = cpumask_of_cpu(0);
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clockevents_register_device(&clockevent_mpu_timer1);
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}
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/*
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* ---------------------------------------------------------------------------
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* MPU timer 2 ... free running 32-bit clock source and scheduler clock
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* ---------------------------------------------------------------------------
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*/
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static unsigned long omap_mpu_timer2_overflows;
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static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
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{
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omap_mpu_timer2_overflows++;
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return IRQ_HANDLED;
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}
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static struct irqaction omap_mpu_timer2_irq = {
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.name = "mpu_timer2",
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.flags = IRQF_DISABLED,
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.handler = omap_mpu_timer2_interrupt,
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};
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static cycle_t mpu_read(void)
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{
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return ~omap_mpu_timer_read(1);
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}
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static struct clocksource clocksource_mpu = {
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.name = "mpu_timer2",
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.rating = 300,
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.read = mpu_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 24,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init omap_init_clocksource(unsigned long rate)
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{
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static char err[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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clocksource_mpu.mult
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= clocksource_khz2mult(rate/1000, clocksource_mpu.shift);
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setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
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omap_mpu_timer_start(1, ~0, 1);
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if (clocksource_register(&clocksource_mpu))
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printk(err, clocksource_mpu.name);
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}
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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unsigned long long sched_clock(void)
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{
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unsigned long ticks = 0 - omap_mpu_timer_read(0);
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unsigned long ticks = 0 - omap_mpu_timer_read(1);
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unsigned long long ticks64;
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ticks64 = omap_mpu_timer1_overflows;
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ticks64 = omap_mpu_timer2_overflows;
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ticks64 <<= 32;
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ticks64 |= ticks;
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@ -225,10 +274,21 @@ unsigned long long sched_clock(void)
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*/
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static void __init omap_timer_init(void)
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{
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omap_init_mpu_timer();
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struct clk *ck_ref = clk_get(NULL, "ck_ref");
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unsigned long rate;
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BUG_ON(IS_ERR(ck_ref));
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rate = clk_get_rate(ck_ref);
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clk_put(ck_ref);
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/* PTV = 0 */
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rate /= 2;
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omap_init_mpu_timer(rate);
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omap_init_clocksource(rate);
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}
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struct sys_timer omap_timer = {
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.init = omap_timer_init,
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.offset = NULL, /* Initialized later */
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};
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@ -11,6 +11,7 @@ choice
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config ARCH_OMAP1
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bool "TI OMAP1"
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select GENERIC_CLOCKEVENTS
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config ARCH_OMAP2
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bool "TI OMAP2"
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@ -156,3 +156,53 @@ static int __init omap_add_serial_console(void)
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return add_preferred_console("ttyS", line, opt);
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}
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console_initcall(omap_add_serial_console);
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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#if defined(CONFIG_ARCH_OMAP16XX)
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#define TIMER_32K_SYNCHRONIZED 0xfffbc410
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#elif defined(CONFIG_ARCH_OMAP24XX)
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#define TIMER_32K_SYNCHRONIZED 0x48004010
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#endif
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#ifdef TIMER_32K_SYNCHRONIZED
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#include <linux/clocksource.h>
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static cycle_t omap_32k_read(void)
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{
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return omap_readl(TIMER_32K_SYNCHRONIZED);
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}
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static struct clocksource clocksource_32k = {
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.name = "32k_counter",
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.rating = 250,
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.read = omap_32k_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init omap_init_clocksource_32k(void)
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{
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static char err[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
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clocksource_32k.mult = clocksource_hz2mult(32768,
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clocksource_32k.shift);
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if (clocksource_register(&clocksource_32k))
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printk(err, clocksource_32k.name);
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}
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return 0;
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}
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arch_initcall(omap_init_clocksource_32k);
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#endif /* TIMER_32K_SYNCHRONIZED */
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@ -42,6 +42,8 @@
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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@ -80,13 +82,13 @@ struct sys_timer omap_timer;
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#define OMAP1_32K_TIMER_TVR 0x00
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#define OMAP1_32K_TIMER_TCR 0x04
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#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
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#define OMAP_32K_TICKS_PER_SEC (32768)
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/*
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* TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
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* so with HZ = 128, TVR = 255.
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*/
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#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
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#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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@ -142,6 +144,28 @@ static inline void omap_32k_timer_ack_irq(void)
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#endif
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static void omap_32k_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_PERIODIC:
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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omap_32k_timer_stop();
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break;
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}
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}
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static struct clock_event_device clockevent_32k_timer = {
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.name = "32k-timer",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.set_mode = omap_32k_timer_set_mode,
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};
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/*
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* The 32KHz synchronized timer is an additional timer on 16xx.
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* It is always running.
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@ -170,15 +194,6 @@ omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
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static unsigned long omap_32k_last_tick = 0;
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/*
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* Returns elapsed usecs since last 32k timer interrupt
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*/
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static unsigned long omap_32k_timer_gettimeoffset(void)
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{
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unsigned long now = omap_32k_sync_timer_read();
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return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
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}
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/*
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* Returns current time from boot in nsecs. It's OK for this to wrap
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* around for now, as it's just a relative time stamp.
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@ -188,95 +203,16 @@ unsigned long long sched_clock(void)
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return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
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}
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/*
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* Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
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* function is also called from other interrupts to remove latency
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* issues with dynamic tick. In the dynamic tick case, we need to lock
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* with irqsave.
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*/
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static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
unsigned long now;
|
||||
|
||||
omap_32k_timer_ack_irq();
|
||||
now = omap_32k_sync_timer_read();
|
||||
|
||||
while ((signed long)(now - omap_32k_last_tick)
|
||||
>= OMAP_32K_TICKS_PER_HZ) {
|
||||
omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
|
||||
timer_tick();
|
||||
}
|
||||
|
||||
/* Restart timer so we don't drift off due to modulo or dynamic tick.
|
||||
* By default we program the next timer to be continuous to avoid
|
||||
* latencies during high system load. During dynamic tick operation the
|
||||
* continuous timer can be overridden from pm_idle to be longer.
|
||||
*/
|
||||
omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id)
|
||||
{
|
||||
return _omap_32k_timer_interrupt(irq, dev_id);
|
||||
}
|
||||
|
||||
static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct clock_event_device *evt = &clockevent_32k_timer;
|
||||
omap_32k_timer_ack_irq();
|
||||
|
||||
write_seqlock_irqsave(&xtime_lock, flags);
|
||||
_omap_32k_timer_interrupt(irq, dev_id);
|
||||
write_sequnlock_irqrestore(&xtime_lock, flags);
|
||||
evt->event_handler(evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
/*
|
||||
* Programs the next timer interrupt needed. Called when dynamic tick is
|
||||
* enabled, and to reprogram the ticks to skip from pm_idle. Note that
|
||||
* we can keep the timer continuous, and don't need to set it to run in
|
||||
* one-shot mode. This is because the timer will get reprogrammed again
|
||||
* after next interrupt.
|
||||
*/
|
||||
void omap_32k_timer_reprogram(unsigned long next_tick)
|
||||
{
|
||||
unsigned long ticks = JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1;
|
||||
unsigned long now = omap_32k_sync_timer_read();
|
||||
unsigned long idled = now - omap_32k_last_tick;
|
||||
|
||||
if (idled + 1 < ticks)
|
||||
ticks -= idled;
|
||||
else
|
||||
ticks = 1;
|
||||
omap_32k_timer_start(ticks);
|
||||
}
|
||||
|
||||
static struct irqaction omap_32k_timer_irq;
|
||||
extern struct timer_update_handler timer_update;
|
||||
|
||||
static int omap_32k_timer_enable_dyn_tick(void)
|
||||
{
|
||||
/* No need to reprogram timer, just use the next interrupt */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_32k_timer_disable_dyn_tick(void)
|
||||
{
|
||||
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dyn_tick_timer omap_dyn_tick_timer = {
|
||||
.enable = omap_32k_timer_enable_dyn_tick,
|
||||
.disable = omap_32k_timer_disable_dyn_tick,
|
||||
.reprogram = omap_32k_timer_reprogram,
|
||||
.handler = omap_32k_timer_handler,
|
||||
};
|
||||
#endif /* CONFIG_NO_IDLE_HZ */
|
||||
|
||||
static struct irqaction omap_32k_timer_irq = {
|
||||
.name = "32KHz timer",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER,
|
||||
|
|
@ -285,13 +221,8 @@ static struct irqaction omap_32k_timer_irq = {
|
|||
|
||||
static __init void omap_init_32k_timer(void)
|
||||
{
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
omap_timer.dyn_tick = &omap_dyn_tick_timer;
|
||||
#endif
|
||||
|
||||
if (cpu_class_is_omap1())
|
||||
setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
|
||||
omap_timer.offset = omap_32k_timer_gettimeoffset;
|
||||
omap_32k_last_tick = omap_32k_sync_timer_read();
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
|
|
@ -308,7 +239,16 @@ static __init void omap_init_32k_timer(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
|
||||
clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
|
||||
NSEC_PER_SEC,
|
||||
clockevent_32k_timer.shift);
|
||||
clockevent_32k_timer.max_delta_ns =
|
||||
clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
|
||||
clockevent_32k_timer.min_delta_ns =
|
||||
clockevent_delta2ns(1, &clockevent_32k_timer);
|
||||
|
||||
clockevent_32k_timer.cpumask = cpumask_of_cpu(0);
|
||||
clockevents_register_device(&clockevent_32k_timer);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -326,5 +266,4 @@ static void __init omap_timer_init(void)
|
|||
|
||||
struct sys_timer omap_timer = {
|
||||
.init = omap_timer_init,
|
||||
.offset = NULL, /* Initialized later */
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue