drm/i915/bdw: Update MI_FLUSH_DW
The code is more verbose than necessary for the reader's sake, hopefully the compiler optimizes away the if. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1670,6 +1670,8 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
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return ret;
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cmd = MI_FLUSH_DW;
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if (INTEL_INFO(ring->dev)->gen >= 8)
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cmd += 1;
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/*
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* Bspec vol 1c.5 - video engine command streamer:
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* "If ENABLED, all TLBs will be invalidated once the flush
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@ -1681,8 +1683,13 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
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MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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if (INTEL_INFO(ring->dev)->gen >= 8) {
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intel_ring_emit(ring, 0); /* upper addr */
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intel_ring_emit(ring, 0); /* value */
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} else {
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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}
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intel_ring_advance(ring);
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return 0;
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}
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@ -1764,6 +1771,8 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
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return ret;
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cmd = MI_FLUSH_DW;
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if (INTEL_INFO(ring->dev)->gen >= 8)
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cmd += 1;
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/*
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* Bspec vol 1c.3 - blitter engine command streamer:
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* "If ENABLED, all TLBs will be invalidated once the flush
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@ -1775,8 +1784,13 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
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MI_FLUSH_DW_OP_STOREDW;
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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if (INTEL_INFO(ring->dev)->gen >= 8) {
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intel_ring_emit(ring, 0); /* upper addr */
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intel_ring_emit(ring, 0); /* value */
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} else {
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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}
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intel_ring_advance(ring);
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if (IS_GEN7(dev) && flush)
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