drm/radeon/hdmi: store info about all AFMT blocks
Introduce special struct radeon_afmt for this purpose. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -156,4 +156,10 @@
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#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
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#define R600_AUDIO_STATUS_BITS 0x73d8
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#define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400)
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#define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400)
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/* DCE3.2 second instance starts at 0x7800 */
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#define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400)
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#define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400)
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#endif
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@ -1057,12 +1057,6 @@
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# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
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# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
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#define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400)
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#define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400)
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/* DCE3.2 second instance starts at 0x7800 */
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#define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400)
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#define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400)
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/*
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* PM4
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*/
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@ -364,7 +364,6 @@ int r600_audio_rate(struct radeon_device *rdev);
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uint8_t r600_audio_status_bits(struct radeon_device *rdev);
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uint8_t r600_audio_category_code(struct radeon_device *rdev);
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void r600_audio_fini(struct radeon_device *rdev);
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void r600_hdmi_init(struct drm_encoder *encoder);
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int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
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void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
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/* r600 blit */
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@ -1225,6 +1225,93 @@ void radeon_update_display_priority(struct radeon_device *rdev)
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}
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/*
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* Allocate hdmi structs and determine register offsets
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*/
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static void radeon_afmt_init(struct radeon_device *rdev)
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{
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int i;
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for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
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rdev->mode_info.afmt[i] = NULL;
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if (ASIC_IS_DCE6(rdev)) {
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/* todo */
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} else if (ASIC_IS_DCE4(rdev)) {
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/* DCE4/5 has 6 audio blocks tied to DIG encoders */
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/* DCE4.1 has 2 audio blocks tied to DIG encoders */
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rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[0]) {
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rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
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rdev->mode_info.afmt[0]->id = 0;
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}
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rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[1]) {
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rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
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rdev->mode_info.afmt[1]->id = 1;
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}
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if (!ASIC_IS_DCE41(rdev)) {
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rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[2]) {
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rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
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rdev->mode_info.afmt[2]->id = 2;
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}
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rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[3]) {
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rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
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rdev->mode_info.afmt[3]->id = 3;
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}
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rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[4]) {
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rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
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rdev->mode_info.afmt[4]->id = 4;
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}
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rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[5]) {
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rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
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rdev->mode_info.afmt[5]->id = 5;
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}
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}
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} else if (ASIC_IS_DCE3(rdev)) {
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/* DCE3.x has 2 audio blocks tied to DIG encoders */
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rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[0]) {
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rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
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rdev->mode_info.afmt[0]->id = 0;
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}
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rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[1]) {
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rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
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rdev->mode_info.afmt[1]->id = 1;
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}
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} else if (ASIC_IS_DCE2(rdev)) {
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/* DCE2 has at least 1 routable audio block */
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rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[0]) {
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rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
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rdev->mode_info.afmt[0]->id = 0;
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}
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/* r6xx has 2 routable audio blocks */
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if (rdev->family >= CHIP_R600) {
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rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
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if (rdev->mode_info.afmt[1]) {
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rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
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rdev->mode_info.afmt[1]->id = 1;
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}
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}
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}
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}
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static void radeon_afmt_fini(struct radeon_device *rdev)
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{
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int i;
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for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
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kfree(rdev->mode_info.afmt[i]);
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rdev->mode_info.afmt[i] = NULL;
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}
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}
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int radeon_modeset_init(struct radeon_device *rdev)
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{
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int i;
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@ -1285,6 +1372,9 @@ int radeon_modeset_init(struct radeon_device *rdev)
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/* initialize hpd */
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radeon_hpd_init(rdev);
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/* setup afmt */
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radeon_afmt_init(rdev);
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/* Initialize power management */
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radeon_pm_init(rdev);
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@ -1301,6 +1391,7 @@ void radeon_modeset_fini(struct radeon_device *rdev)
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radeon_pm_fini(rdev);
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if (rdev->mode_info.mode_config_initialized) {
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radeon_afmt_fini(rdev);
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drm_kms_helper_poll_fini(rdev->ddev);
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radeon_hpd_fini(rdev);
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drm_mode_config_cleanup(rdev->ddev);
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@ -220,12 +220,20 @@ enum radeon_dvo_chip {
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struct radeon_fbdev;
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struct radeon_afmt {
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bool enabled;
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int offset;
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bool last_buffer_filled_status;
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int id;
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};
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struct radeon_mode_info {
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struct atom_context *atom_context;
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struct card_info *atom_card_info;
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enum radeon_connector_table connector_table;
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bool mode_config_initialized;
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struct radeon_crtc *crtcs[6];
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struct radeon_afmt *afmt[6];
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/* DVI-I properties */
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struct drm_property *coherent_mode_property;
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/* DAC enable load detect */
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int dpms_mode;
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uint8_t backlight_level;
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int panel_mode;
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struct radeon_afmt *afmt;
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};
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struct radeon_encoder_atom_dac {
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