drm/i915: fix opregion backlight chip detect and range
BLC_PWM_CTL2 is for 965+ only, so add device model check for legacy backlight control. For native backlight control, it maps the backlight value (0~255) in opregion ASLE[BCLP] to backlight duty cycle (0~max_backlight) and set into control register. It also add support for IGD device, which follows opregion spec. Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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@ -148,6 +148,7 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct opregion_asle *asle = dev_priv->opregion.asle;
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u32 blc_pwm_ctl, blc_pwm_ctl2;
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u32 max_backlight, level, shift;
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if (!(bclp & ASLE_BCLP_VALID))
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return ASLE_BACKLIGHT_FAIL;
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@ -157,14 +158,25 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
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return ASLE_BACKLIGHT_FAIL;
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blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
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blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
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blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2);
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if (blc_pwm_ctl2 & BLM_COMBINATION_MODE)
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if (IS_I965G(dev) && (blc_pwm_ctl2 & BLM_COMBINATION_MODE))
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pci_write_config_dword(dev->pdev, PCI_LBPC, bclp);
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else
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I915_WRITE(BLC_PWM_CTL, blc_pwm_ctl | ((bclp * 0x101)-1));
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else {
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if (IS_IGD(dev)) {
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blc_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
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max_backlight = (blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >>
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BACKLIGHT_MODULATION_FREQ_SHIFT;
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shift = BACKLIGHT_DUTY_CYCLE_SHIFT + 1;
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} else {
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blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
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max_backlight = ((blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >>
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BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
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shift = BACKLIGHT_DUTY_CYCLE_SHIFT;
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}
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level = (bclp * max_backlight) / 255;
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I915_WRITE(BLC_PWM_CTL, blc_pwm_ctl | (level << shift));
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}
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asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
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return 0;
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