staging: comedi: ni_mio_common: Cleans up/clarifies ni_ao_cmd
This patch implements ni_ao_cmd much more closely organized like NI MHDDK examples and DAQ-STC pseudo-code. Adds comments with some more specific references to the DAQ-STC. For stop_src==TRIG_NONE (continuous output mode of entire buffer), the count for the UC counter was corrected to represent the maximum count possible (0xffffff). Prior behavior for stop_src=TRIG_NONE did not actually follow the DAQ-STC. Furthermore, stop_src==TRIG_NONE now correctly uses code specialized for either m-series or e-series devices. It should be noted that stop_src==TRIG_NONE does _not_ with this patch (or with prior behavior in ni_mio_common) actually implement true continuous output. Rather, the output is simply configured to operate as a single buffer output, but where the buffer is as large as is possible with NI-STC hardware. Signed-off-by: Spencer E. Olson <olsonse@umich.edu> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
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d2a6c32a22
commit
080e6795cb
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@ -2912,42 +2912,68 @@ static int ni_ao_inttrig(struct comedi_device *dev,
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return 0;
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}
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static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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/*
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* begin ni_ao_cmd.
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* Organized similar to NI-STC and MHDDK examples.
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* ni_ao_cmd is broken out into configuration sub-routines for clarity.
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*/
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static void ni_ao_cmd_personalize(struct comedi_device *dev,
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const struct comedi_cmd *cmd)
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{
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const struct ni_board_struct *board = dev->board_ptr;
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struct ni_private *devpriv = dev->private;
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const struct comedi_cmd *cmd = &s->async->cmd;
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int bits;
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int i;
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unsigned trigvar;
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unsigned val;
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if (dev->irq == 0) {
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dev_err(dev->class_dev, "cannot run command without an irq\n");
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return -EIO;
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}
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unsigned bits;
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
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ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
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bits =
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/* fast CPU interface--only eseries */
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/* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
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NISTC_AO_PERSONAL_BC_SRC_SEL |
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0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
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/*
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* FIXME: start setting following bit when appropriate. Need to
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* determine whether board is E4 or E1.
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* FROM MHHDK:
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* if board is E4 or E1
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* Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
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* else
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* set it to 1
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*/
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NISTC_AO_PERSONAL_UPDATE_PW |
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/* FIXME: when should we set following bit to zero? */
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NISTC_AO_PERSONAL_TMRDACWR_PW |
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(board->ao_fifo_depth ?
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NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
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;
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#if 0
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/*
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* FIXME:
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* add something like ".has_individual_dacs = 0" to ni_board_struct
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* since, as F Hess pointed out, not all in m series have singles. not
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* sure if e-series all have duals...
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*/
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if (devpriv->is_6xxx) {
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ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
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NI611X_AO_MISC_REG);
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/*
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* F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
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* 6281, verified with bus analyzer.
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*/
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if (devpriv->is_m_series)
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bits |= NISTC_AO_PERSONAL_NUM_DAC;
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#endif
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ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
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bits = 0;
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for (i = 0; i < cmd->chanlist_len; i++) {
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int chan;
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
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}
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chan = CR_CHAN(cmd->chanlist[i]);
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bits |= 1 << chan;
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ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
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}
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ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
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}
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static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
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const struct comedi_cmd *cmd)
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{
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struct ni_private *devpriv = dev->private;
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ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
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/* sync */
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if (cmd->stop_src == TRIG_NONE) {
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devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
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devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
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@ -2957,179 +2983,346 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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}
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ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
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val = devpriv->ao_trigger_select;
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{
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unsigned int trigsel = devpriv->ao_trigger_select;
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switch (cmd->start_src) {
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case TRIG_INT:
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case TRIG_NOW:
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val &= ~(NISTC_AO_TRIG_START1_POLARITY |
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trigsel &= ~(NISTC_AO_TRIG_START1_POLARITY |
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NISTC_AO_TRIG_START1_SEL_MASK);
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val |= NISTC_AO_TRIG_START1_EDGE |
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trigsel |= NISTC_AO_TRIG_START1_EDGE |
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NISTC_AO_TRIG_START1_SYNC;
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break;
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case TRIG_EXT:
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val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
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if (cmd->start_arg & CR_INVERT) {
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/* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
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val |= NISTC_AO_TRIG_START1_POLARITY;
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}
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if (cmd->start_arg & CR_EDGE) {
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trigsel = NISTC_AO_TRIG_START1_SEL(
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CR_CHAN(cmd->start_arg) + 1);
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if (cmd->start_arg & CR_INVERT)
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/*
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* 0=active high, 1=active low.
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* see daq-stc 3-24 (p186)
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*/
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trigsel |= NISTC_AO_TRIG_START1_POLARITY;
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if (cmd->start_arg & CR_EDGE)
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/* 0=edge detection disabled, 1=enabled */
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val |= NISTC_AO_TRIG_START1_EDGE;
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}
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ni_stc_writew(dev, devpriv->ao_trigger_select,
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NISTC_AO_TRIG_SEL_REG);
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trigsel |= NISTC_AO_TRIG_START1_EDGE;
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break;
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default:
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BUG();
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break;
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}
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devpriv->ao_trigger_select = val;
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ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
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devpriv->ao_trigger_select = trigsel;
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ni_stc_writew(dev, devpriv->ao_trigger_select,
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NISTC_AO_TRIG_SEL_REG);
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}
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/* AO_Delayed_START1 = 0, we do not support delayed start...yet */
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/* sync */
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/* select DA_START1 as PFI6/AO_START1 when configured as an output */
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devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
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ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
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}
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static void ni_ao_cmd_set_counters(struct comedi_device *dev,
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const struct comedi_cmd *cmd)
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{
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struct ni_private *devpriv = dev->private;
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/* Not supporting 'waveform staging' or 'local buffer with pauses' */
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
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/*
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* This relies on ao_mode1/(Trigger_Once | Continuous) being set in
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* set_trigger above. It is unclear whether we really need to re-write
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* this register with these values. The mhddk examples for e-series
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* show writing this in both places, but the examples for m-series show
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* a single write in the set_counters function (here).
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*/
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ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
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/* sync (upload number of buffer iterations -1) */
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/* indicate that we want to use BC_Load_A_Register as the source */
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devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
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ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
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if (cmd->stop_src == TRIG_NONE)
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ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
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else
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ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
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/*
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* if the BC_TC interrupt is still issued in spite of UC, BC, UI
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* ignoring BC_TC, then we will need to find a way to ignore that
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* interrupt in continuous mode.
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*/
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ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
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/* sync (issue command to load number of buffer iterations -1) */
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ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
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/* sync (upload number of updates in buffer) */
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/* indicate that we want to use UC_Load_A_Register as the source */
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devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
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ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
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switch (cmd->stop_src) {
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case TRIG_COUNT:
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{
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/*
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* Current behavior is to configure the maximum update count
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* possible when continuous output mode is requested.
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*/
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unsigned int stop_arg = cmd->stop_src == TRIG_COUNT ?
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(cmd->stop_arg & 0xffffff) : 0xffffff;
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if (devpriv->is_m_series) {
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/* this is how the NI example code does it for m-series boards, verified correct with 6259 */
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ni_stc_writel(dev, cmd->stop_arg - 1,
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NISTC_AO_UC_LOADA_REG);
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/*
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* this is how the NI example code does it for m-series
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* boards, verified correct with 6259
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*/
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ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
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/* sync (issue cmd to load number of updates in MISB) */
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
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NISTC_AO_CMD1_REG);
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} else {
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ni_stc_writel(dev, cmd->stop_arg,
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NISTC_AO_UC_LOADA_REG);
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ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
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/* sync (issue cmd to load number of updates in MISB) */
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
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NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, cmd->stop_arg - 1,
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NISTC_AO_UC_LOADA_REG);
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/*
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* sync (upload number of updates-1 in MISB)
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* --eseries only?
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*/
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ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
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}
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break;
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case TRIG_NONE:
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ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
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break;
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default:
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ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
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}
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devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
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}
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static void ni_ao_cmd_set_update(struct comedi_device *dev,
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const struct comedi_cmd *cmd)
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{
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struct ni_private *devpriv = dev->private;
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
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/*
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* zero out these bit fields to be set below. Does an ao-reset do this
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* automatically?
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*/
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devpriv->ao_mode1 &= ~(
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NISTC_AO_MODE1_UI_SRC_MASK |
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NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
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NISTC_AO_MODE1_UI_SRC_POLARITY);
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NISTC_AO_MODE1_UI_SRC_POLARITY |
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NISTC_AO_MODE1_UPDATE_SRC_MASK |
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NISTC_AO_MODE1_UPDATE_SRC_POLARITY
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);
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switch (cmd->scan_begin_src) {
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case TRIG_TIMER:
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devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
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trigvar =
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ni_ns_to_timer(dev, cmd->scan_begin_arg,
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/*
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* NOTE: there are several other ways of configuring internal
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* updates, but we'll only support one for now: using
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* AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
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* START1 and first update, and also w/o local buffer mode w/
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* pauses.
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*/
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/*
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* This is already done above:
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* devpriv->ao_mode1 &= ~(
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* // set UPDATE_Source to UI_TC:
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* NISTC_AO_MODE1_UPDATE_SRC_MASK |
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* // set UPDATE_Source_Polarity to rising (required?)
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* NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
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* // set UI_Source to AO_IN_TIMEBASE1:
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* NISTC_AO_MODE1_UI_SRC_MASK |
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* // set UI_Source_Polarity to rising (required?)
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* NISTC_AO_MODE1_UI_SRC_POLARITY
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* );
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*/
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/*
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* TODO: use ao_ui_clock_source to allow all possible signals
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* to be routed to UI_Source_Select. See tSTC.h for
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* eseries/ni67xx and tMSeries.h for mseries.
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*/
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{
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unsigned trigvar = ni_ns_to_timer(dev,
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cmd->scan_begin_arg,
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CMDF_ROUND_NEAREST);
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/*
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* Wait N TB3 ticks after the start trigger before
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* clocking(N must be >=2).
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*/
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/* following line: 2-1 per STC */
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ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
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ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
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ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD,
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NISTC_AO_CMD1_REG);
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/* following line: N-1 per STC */
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ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG);
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}
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break;
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case TRIG_EXT:
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devpriv->ao_mode1 |=
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NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
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/* FIXME: assert scan_begin_arg != 0, ret failure otherwise */
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devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
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devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
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CR_CHAN(cmd->scan_begin_arg));
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if (cmd->scan_begin_arg & CR_INVERT)
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devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
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devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
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break;
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default:
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BUG();
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break;
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}
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ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
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ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
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devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
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NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
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ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
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if (cmd->scan_end_arg > 1) {
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devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
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ni_stc_writew(dev,
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NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
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NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
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NISTC_AO_OUT_CTRL_REG);
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} else {
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unsigned bits;
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devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
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bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
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if (devpriv->is_m_series || devpriv->is_6xxx) {
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bits |= NISTC_AO_OUT_CTRL_CHANS(0);
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} else {
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bits |=
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NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
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}
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ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
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}
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ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
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/* Configure DAQ-STC for Timed update mode */
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devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
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NISTC_AO_CMD1_DAC0_UPDATE_MODE;
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/* We are not using UPDATE2-->don't have to set DACx_Source_Select */
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ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
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}
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static void ni_ao_cmd_set_channels(struct comedi_device *dev,
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struct comedi_subdevice *s)
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{
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struct ni_private *devpriv = dev->private;
|
||||
const struct comedi_cmd *cmd = &s->async->cmd;
|
||||
unsigned bits = 0;
|
||||
|
||||
ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
|
||||
|
||||
if (devpriv->is_6xxx) {
|
||||
unsigned int i;
|
||||
|
||||
bits = 0;
|
||||
for (i = 0; i < cmd->chanlist_len; ++i) {
|
||||
int chan = CR_CHAN(cmd->chanlist[i]);
|
||||
|
||||
bits |= 1 << chan;
|
||||
ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
|
||||
}
|
||||
ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
|
||||
}
|
||||
|
||||
ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
|
||||
|
||||
if (cmd->scan_end_arg > 1) {
|
||||
devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
|
||||
bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
|
||||
| NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
|
||||
|
||||
} else {
|
||||
devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
|
||||
bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
|
||||
if (devpriv->is_m_series | devpriv->is_6xxx)
|
||||
bits |= NISTC_AO_OUT_CTRL_CHANS(0);
|
||||
else
|
||||
bits |= NISTC_AO_OUT_CTRL_CHANS(
|
||||
CR_CHAN(cmd->chanlist[0]));
|
||||
}
|
||||
|
||||
ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
|
||||
ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
|
||||
|
||||
ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
|
||||
}
|
||||
|
||||
static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
|
||||
const struct comedi_cmd *cmd)
|
||||
{
|
||||
struct ni_private *devpriv = dev->private;
|
||||
|
||||
ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
|
||||
|
||||
devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
|
||||
ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
|
||||
|
||||
/*
|
||||
* Since we are not supporting waveform staging, we ignore these errors:
|
||||
* NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
|
||||
* NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
|
||||
*/
|
||||
|
||||
ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
|
||||
}
|
||||
|
||||
static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
|
||||
{
|
||||
struct ni_private *devpriv = dev->private;
|
||||
|
||||
ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
|
||||
|
||||
devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
|
||||
#ifdef PCIDMA
|
||||
devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
|
||||
#else
|
||||
devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
|
||||
#endif
|
||||
/* NOTE: this is where use_onboard_memory=True would be implemented */
|
||||
devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
|
||||
ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
|
||||
|
||||
bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
|
||||
NISTC_AO_PERSONAL_UPDATE_PW |
|
||||
NISTC_AO_PERSONAL_TMRDACWR_PW;
|
||||
if (board->ao_fifo_depth)
|
||||
bits |= NISTC_AO_PERSONAL_FIFO_ENA;
|
||||
else
|
||||
bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
|
||||
#if 0
|
||||
/*
|
||||
* F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
|
||||
* for 6281, verified with bus analyzer.
|
||||
*/
|
||||
if (devpriv->is_m_series)
|
||||
bits |= NISTC_AO_PERSONAL_NUM_DAC;
|
||||
#endif
|
||||
ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
|
||||
/* enable sending of ao dma requests */
|
||||
/* enable sending of ao fifo requests (dma request) */
|
||||
ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
|
||||
|
||||
ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
|
||||
|
||||
if (cmd->stop_src == TRIG_COUNT) {
|
||||
ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
|
||||
NISTC_INTB_ACK_REG);
|
||||
/* we are not supporting boards with virtual fifos */
|
||||
}
|
||||
|
||||
static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
|
||||
struct comedi_subdevice *s)
|
||||
{
|
||||
if (s->async->cmd.stop_src == TRIG_COUNT)
|
||||
ni_set_bits(dev, NISTC_INTB_ENA_REG,
|
||||
NISTC_INTB_ENA_AO_BC_TC, 1);
|
||||
}
|
||||
|
||||
s->async->inttrig = ni_ao_inttrig;
|
||||
}
|
||||
|
||||
static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
|
||||
{
|
||||
struct ni_private *devpriv = dev->private;
|
||||
const struct comedi_cmd *cmd = &s->async->cmd;
|
||||
|
||||
if (dev->irq == 0) {
|
||||
dev_err(dev->class_dev, "cannot run command without an irq");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* ni_ao_reset should have already been done */
|
||||
ni_ao_cmd_personalize(dev, cmd);
|
||||
/* clearing fifo and preload happens elsewhere */
|
||||
|
||||
ni_ao_cmd_set_trigger(dev, cmd);
|
||||
ni_ao_cmd_set_counters(dev, cmd);
|
||||
ni_ao_cmd_set_update(dev, cmd);
|
||||
ni_ao_cmd_set_channels(dev, s);
|
||||
ni_ao_cmd_set_stop_conditions(dev, cmd);
|
||||
ni_ao_cmd_set_fifo_mode(dev);
|
||||
ni_ao_cmd_set_interrupts(dev, s);
|
||||
|
||||
/*
|
||||
* arm(ing) and star(ting) happen in ni_ao_inttrig, which _must_ be
|
||||
* called for ao commands since 1) TRIG_NOW is not supported and 2) DMA
|
||||
* must be setup and initially written to before arm/start happen.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* end ni_ao_cmd */
|
||||
|
||||
static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
|
||||
struct comedi_cmd *cmd)
|
||||
{
|
||||
|
|
Loading…
Reference in a new issue