[PATCH] forcedeth: Add support for 64bit rings
This forcedeth patch adds high dma support for tx/rx rings. Signed-off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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@ -103,6 +103,7 @@
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* 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
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* 0.49: 10 Dec 2005: Fix tso for large buffers.
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* 0.50: 20 Jan 2006: Add 8021pq tagging support.
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* 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -114,7 +115,7 @@
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* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
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* superfluous timer interrupts from the nic.
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*/
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#define FORCEDETH_VERSION "0.50"
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#define FORCEDETH_VERSION "0.51"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -258,6 +259,8 @@ enum {
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#define NVREG_TXRXCTL_DESC_3 0x02200
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#define NVREG_TXRXCTL_VLANSTRIP 0x00040
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#define NVREG_TXRXCTL_VLANINS 0x00080
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NvRegTxRingPhysAddrHigh = 0x148,
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NvRegRxRingPhysAddrHigh = 0x14C,
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NvRegMIIStatus = 0x180,
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#define NVREG_MIISTAT_ERROR 0x0001
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#define NVREG_MIISTAT_LINKCHANGE 0x0008
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@ -627,6 +630,33 @@ static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
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return 0;
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}
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#define NV_SETUP_RX_RING 0x01
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#define NV_SETUP_TX_RING 0x02
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static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
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{
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struct fe_priv *np = get_nvpriv(dev);
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u8 __iomem *base = get_hwbase(dev);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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if (rxtx_flags & NV_SETUP_RX_RING) {
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writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
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}
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if (rxtx_flags & NV_SETUP_TX_RING) {
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writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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}
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} else {
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if (rxtx_flags & NV_SETUP_RX_RING) {
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writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
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writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
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}
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if (rxtx_flags & NV_SETUP_TX_RING) {
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writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
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writel((u32) (cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
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}
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}
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}
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#define MII_READ (-1)
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/* mii_rw: read/write a register on the PHY.
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*
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@ -1295,10 +1325,7 @@ static void nv_tx_timeout(struct net_device *dev)
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printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
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nv_drain_tx(dev);
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np->next_tx = np->nic_tx = 0;
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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else
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
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setup_hw_rings(dev, NV_SETUP_TX_RING);
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netif_wake_queue(dev);
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}
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@ -1573,11 +1600,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
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}
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/* reinit nic view of the rx queue */
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writel(np->rx_buf_sz, base + NvRegOffloadConfig);
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writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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else
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
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setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
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writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
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base + NvRegRingSizes);
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pci_push(base);
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@ -2310,11 +2333,7 @@ static int nv_open(struct net_device *dev)
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nv_copy_mac_to_hw(dev);
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/* 4) give hw rings */
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writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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else
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
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setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
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writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
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base + NvRegRingSizes);
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@ -2528,8 +2547,15 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
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printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
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pci_name(pci_dev));
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} else {
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if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
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printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
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pci_name(pci_dev));
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goto out_relreg;
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} else {
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dev->features |= NETIF_F_HIGHDMA;
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printk(KERN_INFO "forcedeth: using HIGHDMA\n");
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}
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}
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np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
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} else if (id->driver_data & DEV_HAS_LARGEDESC) {
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