From 08fbd8a5fb24e504ffd278208576afdeefc93a2d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Jul 2020 15:50:09 +0200 Subject: [PATCH] drm/meson: overlay: fix build failure The recent GCC compiler is very picky with the VD_H_START() and AFBC_DEC_PIXEL_BGN_H() macros, triggering a runtime assert error as: In function 'meson_overlay_setup_scaler_params', inlined from 'meson_overlay_atomic_update' at drivers/gpu/drm/meson/meson_overlay.c:542:2: ./include/linux/compiler.h:392:38: error: call to '__compiletime_assert_341' declared with attribute error: FIELD_PREP: value too large for the field drivers/gpu/drm/meson/meson_overlay.c:413:4: note: in expansion of macro 'AFBC_DEC_PIXEL_BGN_H' 413 | AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) | | ^~~~~~~~~~~~~~~~~~~~ ./include/linux/compiler.h:392:38: error: call to '__compiletime_assert_401' declared with attribute error: FIELD_PREP: value too large for the field It's not expected to overflow these fields, but the compiler did find a case where it overflows. We can safely ignore this, so mask the value with the field width. Fixes: e860785d57306 ("drm/meson: overlay: setup overlay for Amlogic FBC") Signed-off-by: Neil Armstrong Acked-by: Daniel Vetter [narmstrong: moved to (value) to avoid precedence issues] Link: https://patchwork.freedesktop.org/patch/msgid/20200707135009.32474-1-narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_overlay.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c index 1f7b2055e012..a8bcc70644df 100644 --- a/drivers/gpu/drm/meson/meson_overlay.c +++ b/drivers/gpu/drm/meson/meson_overlay.c @@ -58,7 +58,8 @@ /* VPP_POSTBLEND_VD1_H_START_END */ #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value) -#define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), value) +#define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \ + ((value) & GENMASK(13, 0))) /* VPP_POSTBLEND_VD1_V_START_END */ #define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value) @@ -144,7 +145,8 @@ #define AFBC_MIF_BLK_END_V(value) FIELD_PREP(GENMASK(11, 0), value) /* AFBC_PIXEL_HOR_SCOPE */ -#define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), value) +#define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), \ + ((value) & GENMASK(12, 0))) #define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value) /* AFBC_PIXEL_VER_SCOPE */