[media] dib0700_devices: Use c99 initializers for structures.
A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @decl@ identifier i1,fld; type T; field list[n] fs; @@ struct i1 { fs T fld; ...}; @bad@ identifier decl.i1,i2; expression e; initializer list[decl.n] is; @@ struct i1 i2 = { is, + .fld = e - e ,...}; // </smpl> Not sure why, but some tables are still using the old way, but at least several of them got fixed. Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
1148f6fdb0
commit
09628b2c21
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@ -220,12 +220,21 @@ static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = {
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};
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static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = {
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60000, 30000,
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1, 8, 3, 1, 0,
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0, 0, 1, 1, 2,
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(3 << 14) | (1 << 12) | (524 << 0),
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0,
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20452225,
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.internal = 60000,
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.sampling = 30000,
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.pll_prediv = 1,
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.pll_ratio = 8,
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.pll_range = 3,
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.pll_reset = 1,
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.pll_bypass = 0,
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.enable_refdiv = 0,
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.bypclk_div = 0,
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.IO_CLK_en_core = 1,
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.ADClkSrc = 1,
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.modulo = 2,
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.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
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.ifreq = 0,
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.timf = 20452225,
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};
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static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = {
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@ -342,57 +351,57 @@ static int stk7700d_tuner_attach(struct dvb_usb_adapter *adap)
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/* STK7700-PH: Digital/Analog Hybrid Tuner, e.h. Cinergy HT USB HE */
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static struct dibx000_agc_config xc3028_agc_config = {
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BAND_VHF | BAND_UHF, /* band_caps */
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.band_caps = BAND_VHF | BAND_UHF,
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/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
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* P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
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* P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
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(0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
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(3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
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712, /* inv_gain */
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21, /* time_stabiliz */
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0, /* alpha_level */
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118, /* thlock */
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0, /* wbd_inv */
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2867, /* wbd_ref */
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0, /* wbd_sel */
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2, /* wbd_alpha */
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0, /* agc1_max */
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0, /* agc1_min */
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39718, /* agc2_max */
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9930, /* agc2_min */
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0, /* agc1_pt1 */
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0, /* agc1_pt2 */
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0, /* agc1_pt3 */
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0, /* agc1_slope1 */
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0, /* agc1_slope2 */
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0, /* agc2_pt1 */
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128, /* agc2_pt2 */
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29, /* agc2_slope1 */
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29, /* agc2_slope2 */
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17, /* alpha_mant */
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27, /* alpha_exp */
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23, /* beta_mant */
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51, /* beta_exp */
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1, /* perform_agc_softsplit */
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.setup = (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
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.inv_gain = 712,
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.time_stabiliz = 21,
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.alpha_level = 0,
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.thlock = 118,
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.wbd_inv = 0,
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.wbd_ref = 2867,
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.wbd_sel = 0,
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.wbd_alpha = 2,
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.agc1_max = 0,
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.agc1_min = 0,
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.agc2_max = 39718,
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.agc2_min = 9930,
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.agc1_pt1 = 0,
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.agc1_pt2 = 0,
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.agc1_pt3 = 0,
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.agc1_slope1 = 0,
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.agc1_slope2 = 0,
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.agc2_pt1 = 0,
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.agc2_pt2 = 128,
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.agc2_slope1 = 29,
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.agc2_slope2 = 29,
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.alpha_mant = 17,
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.alpha_exp = 27,
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.beta_mant = 23,
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.beta_exp = 51,
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.perform_agc_softsplit = 1,
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};
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/* PLL Configuration for COFDM BW_MHz = 8.00 with external clock = 30.00 */
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static struct dibx000_bandwidth_config xc3028_bw_config = {
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60000, 30000, /* internal, sampling */
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1, 8, 3, 1, 0, /* pll_cfg: prediv, ratio, range, reset, bypass */
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0, 0, 1, 1, 0, /* misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc,
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modulo */
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(3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
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(1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
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20452225, /* timf */
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30000000, /* xtal_hz */
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.internal = 60000,
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.sampling = 30000,
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.pll_prediv = 1,
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.pll_ratio = 8,
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.pll_range = 3,
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.pll_reset = 1,
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.pll_bypass = 0,
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.enable_refdiv = 0,
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.bypclk_div = 0,
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.IO_CLK_en_core = 1,
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.ADClkSrc = 1,
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.modulo = 0,
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.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
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.ifreq = (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
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.timf = 20452225,
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.xtal_hz = 30000000,
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};
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static struct dib7000p_config stk7700ph_dib7700_xc3028_config = {
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@ -614,59 +623,55 @@ static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = {
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};
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static struct dibx000_agc_config stk7700p_7000p_mt2060_agc_config = {
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BAND_UHF | BAND_VHF,
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.band_caps = BAND_UHF | BAND_VHF,
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/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
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* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
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(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
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| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
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712,
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41,
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0,
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118,
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0,
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4095,
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0,
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0,
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42598,
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16384,
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42598,
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0,
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0,
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137,
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255,
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0,
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255,
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0,
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0,
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0,
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41,
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15,
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25,
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28,
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48,
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0,
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.setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
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.inv_gain = 712,
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.time_stabiliz = 41,
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.alpha_level = 0,
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.thlock = 118,
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.wbd_inv = 0,
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.wbd_ref = 4095,
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.wbd_sel = 0,
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.wbd_alpha = 0,
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.agc1_max = 42598,
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.agc1_min = 16384,
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.agc2_max = 42598,
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.agc2_min = 0,
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.agc1_pt1 = 0,
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.agc1_pt2 = 137,
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.agc1_pt3 = 255,
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.agc1_slope1 = 0,
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.agc1_slope2 = 255,
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.agc2_pt1 = 0,
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.agc2_pt2 = 0,
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.agc2_slope1 = 0,
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.agc2_slope2 = 41,
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.alpha_mant = 15,
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.alpha_exp = 25,
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.beta_mant = 28,
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.beta_exp = 48,
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.perform_agc_softsplit = 0,
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};
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static struct dibx000_bandwidth_config stk7700p_pll_config = {
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60000, 30000,
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1, 8, 3, 1, 0,
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0, 0, 1, 1, 0,
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(3 << 14) | (1 << 12) | (524 << 0),
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60258167,
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20452225,
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30000000,
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.internal = 60000,
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.sampling = 30000,
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.pll_prediv = 1,
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.pll_ratio = 8,
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.pll_range = 3,
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.pll_reset = 1,
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.pll_bypass = 0,
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.enable_refdiv = 0,
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.bypclk_div = 0,
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.IO_CLK_en_core = 1,
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.ADClkSrc = 1,
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.modulo = 0,
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.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
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.ifreq = 60258167,
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.timf = 20452225,
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.xtal_hz = 30000000,
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};
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static struct dib7000m_config stk7700p_dib7000m_config = {
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@ -758,45 +763,36 @@ static int stk7700p_tuner_attach(struct dvb_usb_adapter *adap)
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/* DIB7070 generic */
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static struct dibx000_agc_config dib7070_agc_config = {
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BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
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.band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
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/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
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* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
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(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
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| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
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600,
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10,
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0,
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118,
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0,
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3530,
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1,
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5,
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65535,
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0,
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65535,
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0,
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0,
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40,
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183,
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206,
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255,
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72,
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152,
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88,
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90,
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17,
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27,
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23,
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51,
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0,
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.setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
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.inv_gain = 600,
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.time_stabiliz = 10,
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.alpha_level = 0,
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.thlock = 118,
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.wbd_inv = 0,
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.wbd_ref = 3530,
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.wbd_sel = 1,
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.wbd_alpha = 5,
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.agc1_max = 65535,
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.agc1_min = 0,
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.agc2_max = 65535,
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.agc2_min = 0,
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.agc1_pt1 = 0,
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.agc1_pt2 = 40,
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.agc1_pt3 = 183,
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.agc1_slope1 = 206,
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.agc1_slope2 = 255,
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.agc2_pt1 = 72,
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.agc2_pt2 = 152,
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.agc2_slope1 = 88,
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.agc2_slope2 = 90,
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.alpha_mant = 17,
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.alpha_exp = 27,
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.beta_mant = 23,
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.beta_exp = 51,
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.perform_agc_softsplit = 0,
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};
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static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
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@ -952,13 +948,22 @@ static int stk70x0p_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
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}
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static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
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60000, 15000,
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1, 20, 3, 1, 0,
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0, 0, 1, 1, 2,
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(3 << 14) | (1 << 12) | (524 << 0),
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(0 << 25) | 0,
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20452225,
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12000000,
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.internal = 60000,
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.sampling = 15000,
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.pll_prediv = 1,
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.pll_ratio = 20,
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.pll_range = 3,
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.pll_reset = 1,
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.pll_bypass = 0,
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.enable_refdiv = 0,
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.bypclk_div = 0,
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.IO_CLK_en_core = 1,
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.ADClkSrc = 1,
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.modulo = 2,
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.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
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.ifreq = (0 << 25) | 0,
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.timf = 20452225,
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.xtal_hz = 12000000,
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};
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static struct dib7000p_config dib7070p_dib7000p_config = {
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@ -1169,14 +1174,22 @@ static struct dibx000_agc_config dib807x_agc_config[2] = {
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};
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static struct dibx000_bandwidth_config dib807x_bw_config_12_mhz = {
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60000, 15000, /* internal, sampling*/
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1, 20, 3, 1, 0, /* pll_cfg: prediv, ratio, range, reset, bypass*/
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0, 0, 1, 1, 2, /* misc: refdiv, bypclk_div, IO_CLK_en_core,
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ADClkSrc, modulo */
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(3 << 14) | (1 << 12) | (599 << 0), /* sad_cfg: refsel, sel, freq_15k*/
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(0 << 25) | 0, /* ifreq = 0.000000 MHz*/
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18179755, /* timf*/
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12000000, /* xtal_hz*/
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.internal = 60000,
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.sampling = 15000,
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.pll_prediv = 1,
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.pll_ratio = 20,
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.pll_range = 3,
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.pll_reset = 1,
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.pll_bypass = 0,
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.enable_refdiv = 0,
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.bypclk_div = 0,
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.IO_CLK_en_core = 1,
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.ADClkSrc = 1,
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.modulo = 2,
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.sad_cfg = (3 << 14) | (1 << 12) | (599 << 0), /* sad_cfg: refsel, sel, freq_15k*/
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.ifreq = (0 << 25) | 0, /* ifreq = 0.000000 MHz*/
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.timf = 18179755,
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.xtal_hz = 12000000,
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};
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static struct dib8000_config dib807x_dib8000_config[2] = {
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@ -1921,13 +1934,22 @@ static struct dibx000_agc_config dib8096p_agc_config[2] = {
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};
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static struct dibx000_bandwidth_config dib8096p_clock_config_12_mhz = {
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108000, 13500,
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1, 9, 1, 0, 0,
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0, 0, 0, 0, 2,
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(3 << 14) | (1 << 12) | (524 << 0),
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(0 << 25) | 0,
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20199729,
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12000000,
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.internal = 108000,
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.sampling = 13500,
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.pll_prediv = 1,
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.pll_ratio = 9,
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.pll_range = 1,
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.pll_reset = 0,
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.pll_bypass = 0,
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.enable_refdiv = 0,
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.bypclk_div = 0,
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.IO_CLK_en_core = 0,
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.ADClkSrc = 0,
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.modulo = 2,
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.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
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.ifreq = (0 << 25) | 0,
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.timf = 20199729,
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.xtal_hz = 12000000,
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};
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static struct dib8000_config tfe8096p_dib8000_config = {
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@ -2724,13 +2746,22 @@ static struct dibx000_agc_config dib7090_agc_config[2] = {
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};
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static struct dibx000_bandwidth_config dib7090_clock_config_12_mhz = {
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60000, 15000,
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1, 5, 0, 0, 0,
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0, 0, 1, 1, 2,
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(3 << 14) | (1 << 12) | (524 << 0),
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(0 << 25) | 0,
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20452225,
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15000000,
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.internal = 60000,
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.sampling = 15000,
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.pll_prediv = 1,
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.pll_ratio = 5,
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.pll_range = 0,
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.pll_reset = 0,
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.pll_bypass = 0,
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.enable_refdiv = 0,
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.bypclk_div = 0,
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.IO_CLK_en_core = 1,
|
||||
.ADClkSrc = 1,
|
||||
.modulo = 2,
|
||||
.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
|
||||
.ifreq = (0 << 25) | 0,
|
||||
.timf = 20452225,
|
||||
.xtal_hz = 15000000,
|
||||
};
|
||||
|
||||
static struct dib7000p_config nim7090_dib7000p_config = {
|
||||
|
|
@ -3498,14 +3529,22 @@ static struct dibx000_agc_config stk7700p_7000p_xc4000_agc_config = {
|
|||
};
|
||||
|
||||
static struct dibx000_bandwidth_config stk7700p_xc4000_pll_config = {
|
||||
60000, 30000, /* internal, sampling */
|
||||
1, 8, 3, 1, 0, /* pll_cfg: prediv, ratio, range, reset, bypass */
|
||||
0, 0, 1, 1, 0, /* misc: refdiv, bypclk_div, IO_CLK_en_core, */
|
||||
/* ADClkSrc, modulo */
|
||||
(3 << 14) | (1 << 12) | 524, /* sad_cfg: refsel, sel, freq_15k */
|
||||
39370534, /* ifreq */
|
||||
20452225, /* timf */
|
||||
30000000 /* xtal */
|
||||
.internal = 60000,
|
||||
.sampling = 30000,
|
||||
.pll_prediv = 1,
|
||||
.pll_ratio = 8,
|
||||
.pll_range = 3,
|
||||
.pll_reset = 1,
|
||||
.pll_bypass = 0,
|
||||
.enable_refdiv = 0,
|
||||
.bypclk_div = 0,
|
||||
.IO_CLK_en_core = 1,
|
||||
.ADClkSrc = 1,
|
||||
.modulo = 0,
|
||||
.sad_cfg = (3 << 14) | (1 << 12) | 524, /* sad_cfg: refsel, sel, freq_15k */
|
||||
.ifreq = 39370534,
|
||||
.timf = 20452225,
|
||||
.xtal_hz = 30000000
|
||||
};
|
||||
|
||||
/* FIXME: none of these inputs are validated yet */
|
||||
|
|
|
|||
Loading…
Reference in a new issue