drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
Register MIPI_CLOCK_CTRL is applicable only for BXT platform. Future platform have other registers to program the escape clock dividers. Signed-off-by: Deepak M <m.deepak@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-6-git-send-email-madhav.chauhan@intel.com
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@ -489,8 +489,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
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POSTING_READ(BXT_DSI_PLL_CTL);
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POSTING_READ(BXT_DSI_PLL_CTL);
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/* Program TX, RX, Dphy clocks */
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/* Program TX, RX, Dphy clocks */
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if (IS_BROXTON(dev_priv)) {
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for_each_dsi_port(port, intel_dsi->ports)
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for_each_dsi_port(port, intel_dsi->ports)
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bxt_dsi_program_clocks(encoder->base.dev, port, config);
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bxt_dsi_program_clocks(encoder->base.dev, port, config);
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}
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/* Enable DSI PLL */
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/* Enable DSI PLL */
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val = I915_READ(BXT_DSI_PLL_ENABLE);
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val = I915_READ(BXT_DSI_PLL_ENABLE);
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@ -554,19 +556,22 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
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bxt_disable_dsi_pll(encoder);
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bxt_disable_dsi_pll(encoder);
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}
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}
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static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
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static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
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enum port port)
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{
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{
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u32 tmp;
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u32 tmp;
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struct drm_device *dev = encoder->base.dev;
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(dev);
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/* Clear old configurations */
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/* Clear old configurations */
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if (IS_BROXTON(dev_priv)) {
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tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
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tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
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tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
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tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
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tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
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I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
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I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
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}
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I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
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I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
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}
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}
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@ -575,7 +580,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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if (IS_GEN9_LP(dev_priv))
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if (IS_GEN9_LP(dev_priv))
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bxt_dsi_reset_clocks(encoder, port);
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gen9lp_dsi_reset_clocks(encoder, port);
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else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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vlv_dsi_reset_clocks(encoder, port);
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vlv_dsi_reset_clocks(encoder, port);
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}
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}
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