ARM: PL08x: assign ccfg DMA request signal in prep_phy_channel()
There is no need to wait until we start processing a tx descriptor before setting up the DMA request selection in the ccfg register. We know which channel and request will be used in prep_phy_channel(), so setup the ccfg request selection at txd creation time in prep_phy_channel(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -194,18 +194,10 @@ static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_phy_chan *phychan = plchan->phychan;
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struct pl08x_phy_chan *phychan = plchan->phychan;
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struct pl08x_lli *lli = &txd->llis_va[0];
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struct pl08x_lli *lli = &txd->llis_va[0];
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u32 val, ccfg = txd->ccfg;
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u32 val;
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plchan->at = txd;
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plchan->at = txd;
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/* Assign the flow control signal to this channel */
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if (txd->direction == DMA_TO_DEVICE)
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/* Select signal as destination */
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ccfg |= phychan->signal << PL080_CONFIG_DST_SEL_SHIFT;
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else if (txd->direction == DMA_FROM_DEVICE)
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/* Select signal as source */
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ccfg |= phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
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/* Wait for channel inactive */
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/* Wait for channel inactive */
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while (pl08x_phy_channel_busy(phychan))
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while (pl08x_phy_channel_busy(phychan))
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cpu_relax();
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cpu_relax();
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@ -214,13 +206,13 @@ static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
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"WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
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"WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
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"clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
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"clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
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phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
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phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
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ccfg);
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txd->ccfg);
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writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
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writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
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writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
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writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
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writel(lli->lli, phychan->base + PL080_CH_LLI);
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writel(lli->lli, phychan->base + PL080_CH_LLI);
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writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
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writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
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writel(ccfg, phychan->base + PL080_CH_CONFIG);
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writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
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/* Enable the DMA channel */
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/* Enable the DMA channel */
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/* Do not access config register until channel shows as disabled */
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/* Do not access config register until channel shows as disabled */
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@ -1001,6 +993,12 @@ static int prep_phy_channel(struct pl08x_dma_chan *plchan,
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return -EBUSY;
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return -EBUSY;
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}
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}
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ch->signal = ret;
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ch->signal = ret;
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/* Assign the flow control signal to this channel */
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if (txd->direction == DMA_TO_DEVICE)
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txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
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else if (txd->direction == DMA_FROM_DEVICE)
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txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
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}
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}
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dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
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dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
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