sparc64: Abstract away PIC register accesses.
And, like for the PCR, allow indexing of different PIC register numbers. This also removes all of the non-__KERNEL__ bits from asm/perfctr.h, nothing kernel side should include it any more. Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
David S. Miller
parent
0bab20ba4c
commit
09d053c797
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@ -2,8 +2,10 @@
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#define __PCR_H
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struct pcr_ops {
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u64 (*read)(unsigned long);
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void (*write)(unsigned long, u64);
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u64 (*read_pcr)(unsigned long);
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void (*write_pcr)(unsigned long, u64);
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u64 (*read_pic)(unsigned long);
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void (*write_pic)(unsigned long, u64);
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};
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extern const struct pcr_ops *pcr_ops;
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@ -54,11 +54,6 @@ enum perfctr_opcode {
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PERFCTR_GETPCR
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};
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/* I don't want the kernel's namespace to be polluted with this
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* stuff when this file is included. --DaveM
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*/
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#ifndef __KERNEL__
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#define PRIV 0x00000001
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#define SYS 0x00000002
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#define USR 0x00000004
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@ -168,29 +163,4 @@ struct vcounter_struct {
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unsigned long long vcnt1;
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};
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#else /* !(__KERNEL__) */
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#ifndef CONFIG_SPARC32
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/* Performance counter register access. */
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#define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
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#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
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#define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
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/* Blackbird errata workaround. See commentary in
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* arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
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* for more information.
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*/
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#define write_pic(__p) \
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__asm__ __volatile__("ba,pt %%xcc, 99f\n\t" \
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" nop\n\t" \
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".align 64\n" \
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"99:wr %0, 0x0, %%pic\n\t" \
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"rd %%pic, %%g0" : : "r" (__p))
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#define reset_pic() write_pic(0)
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#endif /* !CONFIG_SPARC32 */
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#endif /* !(__KERNEL__) */
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#endif /* !(PERF_COUNTER_API) */
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@ -22,7 +22,6 @@
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#include <asm/perf_event.h>
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#include <asm/ptrace.h>
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#include <asm/pcr.h>
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#include <asm/perfctr.h>
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#include "kstack.h"
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@ -109,7 +108,7 @@ notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs)
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pt_regs_trap_type(regs), SIGINT) == NOTIFY_STOP)
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touched = 1;
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else
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pcr_ops->write(0, PCR_PIC_PRIV);
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pcr_ops->write_pcr(0, PCR_PIC_PRIV);
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sum = local_cpu_data().irq0_irqs;
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if (__get_cpu_var(nmi_touch)) {
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@ -126,8 +125,8 @@ notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs)
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__this_cpu_write(alert_counter, 0);
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}
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if (__get_cpu_var(wd_enabled)) {
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write_pic(picl_value(nmi_hz));
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pcr_ops->write(0, pcr_enable);
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pcr_ops->write_pic(0, picl_value(nmi_hz));
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pcr_ops->write_pcr(0, pcr_enable);
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}
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restore_hardirq_stack(orig_sp);
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@ -166,7 +165,7 @@ static void report_broken_nmi(int cpu, int *prev_nmi_count)
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void stop_nmi_watchdog(void *unused)
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{
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pcr_ops->write(0, PCR_PIC_PRIV);
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pcr_ops->write_pcr(0, PCR_PIC_PRIV);
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__get_cpu_var(wd_enabled) = 0;
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atomic_dec(&nmi_active);
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}
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@ -223,10 +222,10 @@ void start_nmi_watchdog(void *unused)
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__get_cpu_var(wd_enabled) = 1;
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atomic_inc(&nmi_active);
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pcr_ops->write(0, PCR_PIC_PRIV);
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write_pic(picl_value(nmi_hz));
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pcr_ops->write_pcr(0, PCR_PIC_PRIV);
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pcr_ops->write_pic(0, picl_value(nmi_hz));
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pcr_ops->write(0, pcr_enable);
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pcr_ops->write_pcr(0, pcr_enable);
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}
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static void nmi_adjust_hz_one(void *unused)
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@ -234,10 +233,10 @@ static void nmi_adjust_hz_one(void *unused)
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if (!__get_cpu_var(wd_enabled))
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return;
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pcr_ops->write(0, PCR_PIC_PRIV);
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write_pic(picl_value(nmi_hz));
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pcr_ops->write_pcr(0, PCR_PIC_PRIV);
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pcr_ops->write_pic(0, picl_value(nmi_hz));
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pcr_ops->write(0, pcr_enable);
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pcr_ops->write_pcr(0, pcr_enable);
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}
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void nmi_adjust_hz(unsigned int new_hz)
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@ -14,7 +14,6 @@
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#include <asm/pcr.h>
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#include <asm/nmi.h>
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#include <asm/spitfire.h>
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#include <asm/perfctr.h>
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/* This code is shared between various users of the performance
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* counters. Users will be oprofile, pseudo-NMI watchdog, and the
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@ -65,19 +64,45 @@ static u64 direct_pcr_read(unsigned long reg_num)
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u64 val;
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WARN_ON_ONCE(reg_num != 0);
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read_pcr(val);
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__asm__ __volatile__("rd %%pcr, %0" : "=r" (val));
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return val;
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}
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static void direct_pcr_write(unsigned long reg_num, u64 val)
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{
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WARN_ON_ONCE(reg_num != 0);
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write_pcr(val);
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__asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val));
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}
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static u64 direct_pic_read(unsigned long reg_num)
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{
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u64 val;
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WARN_ON_ONCE(reg_num != 0);
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__asm__ __volatile__("rd %%pic, %0" : "=r" (val));
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return val;
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}
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static void direct_pic_write(unsigned long reg_num, u64 val)
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{
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WARN_ON_ONCE(reg_num != 0);
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/* Blackbird errata workaround. See commentary in
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* arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
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* for more information.
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*/
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__asm__ __volatile__("ba,pt %%xcc, 99f\n\t"
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" nop\n\t"
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".align 64\n"
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"99:wr %0, 0x0, %%pic\n\t"
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"rd %%pic, %%g0" : : "r" (val));
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}
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static const struct pcr_ops direct_pcr_ops = {
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.read = direct_pcr_read,
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.write = direct_pcr_write,
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.read_pcr = direct_pcr_read,
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.write_pcr = direct_pcr_write,
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.read_pic = direct_pic_read,
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.write_pic = direct_pic_write,
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};
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static void n2_pcr_write(unsigned long reg_num, u64 val)
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@ -88,14 +113,16 @@ static void n2_pcr_write(unsigned long reg_num, u64 val)
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if (val & PCR_N2_HTRACE) {
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ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
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if (ret != HV_EOK)
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write_pcr(val);
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direct_pcr_write(reg_num, val);
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} else
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write_pcr(val);
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direct_pcr_write(reg_num, val);
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}
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static const struct pcr_ops n2_pcr_ops = {
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.read = direct_pcr_read,
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.write = n2_pcr_write,
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.read_pcr = direct_pcr_read,
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.write_pcr = n2_pcr_write,
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.read_pic = direct_pic_read,
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.write_pic = direct_pic_write,
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};
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static unsigned long perf_hsvc_group;
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@ -25,7 +25,6 @@
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#include <linux/atomic.h>
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#include <asm/nmi.h>
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#include <asm/pcr.h>
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#include <asm/perfctr.h>
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#include <asm/cacheflush.h>
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#include "kernel.h"
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@ -564,7 +563,7 @@ static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_
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val |= hwc->config;
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cpuc->pcr = val;
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pcr_ops->write(0, cpuc->pcr);
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pcr_ops->write_pcr(0, cpuc->pcr);
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}
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static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
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@ -578,14 +577,14 @@ static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw
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val |= nop;
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cpuc->pcr = val;
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pcr_ops->write(0, cpuc->pcr);
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pcr_ops->write_pcr(0, cpuc->pcr);
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}
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static u32 read_pmc(int idx)
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{
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u64 val;
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read_pic(val);
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val = pcr_ops->read_pic(0);
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if (idx == PIC_UPPER_INDEX)
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val >>= 32;
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@ -603,10 +602,10 @@ static void write_pmc(int idx, u64 val)
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mask = ((u64) 0xffffffff) << shift;
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val <<= shift;
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read_pic(pic);
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pic = pcr_ops->read_pic(0);
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pic &= ~mask;
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pic |= val;
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write_pic(pic);
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pcr_ops->write_pic(0, pic);
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}
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static u64 sparc_perf_event_update(struct perf_event *event,
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@ -736,7 +735,7 @@ static void sparc_pmu_enable(struct pmu *pmu)
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cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
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}
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pcr_ops->write(0, cpuc->pcr);
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pcr_ops->write_pcr(0, cpuc->pcr);
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}
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static void sparc_pmu_disable(struct pmu *pmu)
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@ -755,7 +754,7 @@ static void sparc_pmu_disable(struct pmu *pmu)
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sparc_pmu->hv_bit | sparc_pmu->irq_bit);
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cpuc->pcr = val;
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pcr_ops->write(0, cpuc->pcr);
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pcr_ops->write_pcr(0, cpuc->pcr);
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}
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static int active_event_index(struct cpu_hw_events *cpuc,
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@ -856,7 +855,7 @@ static void perf_stop_nmi_watchdog(void *unused)
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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stop_nmi_watchdog(NULL);
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cpuc->pcr = pcr_ops->read(0);
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cpuc->pcr = pcr_ops->read_pcr(0);
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}
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void perf_event_grab_pmc(void)
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@ -1264,8 +1263,8 @@ void perf_event_print_debug(void)
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cpu = smp_processor_id();
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pcr = pcr_ops->read(0);
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read_pic(pic);
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pcr = pcr_ops->read_pcr(0);
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pic = pcr_ops->read_pic(0);
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pr_info("\n");
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pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
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@ -1306,7 +1305,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
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* overflow so we don't lose any events.
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*/
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if (sparc_pmu->irq_bit)
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pcr_ops->write(0, cpuc->pcr);
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pcr_ops->write_pcr(0, cpuc->pcr);
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for (i = 0; i < cpuc->n_events; i++) {
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struct perf_event *event = cpuc->event[i];
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