Merge branch 'for-2.6.40' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6 into topic/asoc
This commit is contained in:
commit
09f68072b3
19
Documentation/ABI/testing/sysfs-driver-samsung-laptop
Normal file
19
Documentation/ABI/testing/sysfs-driver-samsung-laptop
Normal file
|
@ -0,0 +1,19 @@
|
|||
What: /sys/devices/platform/samsung/performance_level
|
||||
Date: January 1, 2010
|
||||
KernelVersion: 2.6.33
|
||||
Contact: Greg Kroah-Hartman <gregkh@suse.de>
|
||||
Description: Some Samsung laptops have different "performance levels"
|
||||
that are can be modified by a function key, and by this
|
||||
sysfs file. These values don't always make a whole lot
|
||||
of sense, but some users like to modify them to keep
|
||||
their fans quiet at all costs. Reading from this file
|
||||
will show the current performance level. Writing to the
|
||||
file can change this value.
|
||||
Valid options:
|
||||
"silent"
|
||||
"normal"
|
||||
"overclock"
|
||||
Note that not all laptops support all of these options.
|
||||
Specifically, not all support the "overclock" option,
|
||||
and it's still unknown if this value even changes
|
||||
anything, other than making the user feel a bit better.
|
31
Documentation/ABI/testing/sysfs-platform-asus-wmi
Normal file
31
Documentation/ABI/testing/sysfs-platform-asus-wmi
Normal file
|
@ -0,0 +1,31 @@
|
|||
What: /sys/devices/platform/<platform>/cpufv
|
||||
Date: Oct 2010
|
||||
KernelVersion: 2.6.37
|
||||
Contact: "Corentin Chary" <corentincj@iksaif.net>
|
||||
Description:
|
||||
Change CPU clock configuration (write-only).
|
||||
There are three available clock configuration:
|
||||
* 0 -> Super Performance Mode
|
||||
* 1 -> High Performance Mode
|
||||
* 2 -> Power Saving Mode
|
||||
|
||||
What: /sys/devices/platform/<platform>/camera
|
||||
Date: Jan 2010
|
||||
KernelVersion: 2.6.39
|
||||
Contact: "Corentin Chary" <corentincj@iksaif.net>
|
||||
Description:
|
||||
Control the camera. 1 means on, 0 means off.
|
||||
|
||||
What: /sys/devices/platform/<platform>/cardr
|
||||
Date: Jan 2010
|
||||
KernelVersion: 2.6.39
|
||||
Contact: "Corentin Chary" <corentincj@iksaif.net>
|
||||
Description:
|
||||
Control the card reader. 1 means on, 0 means off.
|
||||
|
||||
What: /sys/devices/platform/<platform>/touchpad
|
||||
Date: Jan 2010
|
||||
KernelVersion: 2.6.39
|
||||
Contact: "Corentin Chary" <corentincj@iksaif.net>
|
||||
Description:
|
||||
Control the card touchpad. 1 means on, 0 means off.
|
|
@ -1,10 +0,0 @@
|
|||
What: /sys/devices/platform/eeepc-wmi/cpufv
|
||||
Date: Oct 2010
|
||||
KernelVersion: 2.6.37
|
||||
Contact: "Corentin Chary" <corentincj@iksaif.net>
|
||||
Description:
|
||||
Change CPU clock configuration (write-only).
|
||||
There are three available clock configuration:
|
||||
* 0 -> Super Performance Mode
|
||||
* 1 -> High Performance Mode
|
||||
* 2 -> Power Saving Mode
|
|
@ -14,7 +14,8 @@ Some models report hotkeys through the SNC or SPIC devices, such events are
|
|||
reported both through the ACPI subsystem as acpi events and through the INPUT
|
||||
subsystem. See the logs of acpid or /proc/acpi/event and
|
||||
/proc/bus/input/devices to find out what those events are and which input
|
||||
devices are created by the driver.
|
||||
devices are created by the driver. Additionally, loading the driver with the
|
||||
debug option will report all events in the kernel log.
|
||||
|
||||
Backlight control:
|
||||
------------------
|
||||
|
@ -64,6 +65,16 @@ powers off the sound card,
|
|||
# echo "1" > /sys/devices/platform/sony-laptop/audiopower
|
||||
powers on the sound card.
|
||||
|
||||
|
||||
RFkill control:
|
||||
---------------
|
||||
More recent Vaio models expose a consistent set of ACPI methods to
|
||||
control radio frequency emitting devices. If you are a lucky owner of
|
||||
such a laptop you will find the necessary rfkill devices under
|
||||
/sys/class/rfkill. Check those starting with sony-* in
|
||||
# grep . /sys/class/rfkill/*/{state,name}
|
||||
|
||||
|
||||
Development:
|
||||
------------
|
||||
|
||||
|
@ -75,8 +86,21 @@ pass the option 'debug=1'.
|
|||
REPEAT: DON'T DO THIS IF YOU DON'T LIKE RISKY BUSINESS.
|
||||
|
||||
In your kernel logs you will find the list of all ACPI methods
|
||||
the SNC device has on your laptop. You can see the GCDP/GCDP methods
|
||||
used to pwer on/off the CD drive, but there are others.
|
||||
the SNC device has on your laptop.
|
||||
|
||||
* For new models you will see a long list of meaningless method names,
|
||||
reading the DSDT table source should reveal that:
|
||||
(1) the SNC device uses an internal capability lookup table
|
||||
(2) SN00 is used to find values in the lookup table
|
||||
(3) SN06 and SN07 are used to call into the real methods based on
|
||||
offsets you can obtain iterating the table using SN00
|
||||
(4) SN02 used to enable events.
|
||||
Some values in the capability lookup table are more or less known, see
|
||||
the code for all sony_call_snc_handle calls, others are more obscure.
|
||||
|
||||
* For old models you can see the GCDP/GCDP methods used to pwer on/off
|
||||
the CD drive, but there are others and they are usually different from
|
||||
model to model.
|
||||
|
||||
I HAVE NO IDEA WHAT THOSE METHODS DO.
|
||||
|
||||
|
@ -108,9 +132,8 @@ Bugs/Limitations:
|
|||
laptop, including permanent damage.
|
||||
|
||||
* The sony-laptop and sonypi drivers do not interact at all. In the
|
||||
future, sonypi could use sony-laptop to do (part of) its business.
|
||||
future, sonypi will be removed and replaced by sony-laptop.
|
||||
|
||||
* spicctrl, which is the userspace tool used to communicate with the
|
||||
sonypi driver (through /dev/sonypi) does not try to use the
|
||||
sony-laptop driver. In the future, spicctrl could try sonypi first,
|
||||
and if it isn't present, try sony-laptop instead.
|
||||
sonypi driver (through /dev/sonypi) is deprecated as well since all
|
||||
its features are now available under the sysfs tree via sony-laptop.
|
||||
|
|
30
MAINTAINERS
30
MAINTAINERS
|
@ -1157,14 +1157,14 @@ S: Maintained
|
|||
F: Documentation/hwmon/asc7621
|
||||
F: drivers/hwmon/asc7621.c
|
||||
|
||||
ASUS ACPI EXTRAS DRIVER
|
||||
ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
|
||||
M: Corentin Chary <corentincj@iksaif.net>
|
||||
M: Karol Kozimor <sziwan@users.sourceforge.net>
|
||||
L: acpi4asus-user@lists.sourceforge.net
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
W: http://acpi4asus.sf.net
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/asus_acpi.c
|
||||
F: drivers/platform/x86/asus*.c
|
||||
F: drivers/platform/x86/eeepc*.c
|
||||
|
||||
ASUS ASB100 HARDWARE MONITOR DRIVER
|
||||
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
|
||||
|
@ -1172,14 +1172,6 @@ L: lm-sensors@lm-sensors.org
|
|||
S: Maintained
|
||||
F: drivers/hwmon/asb100.c
|
||||
|
||||
ASUS LAPTOP EXTRAS DRIVER
|
||||
M: Corentin Chary <corentincj@iksaif.net>
|
||||
L: acpi4asus-user@lists.sourceforge.net
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
W: http://acpi4asus.sf.net
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/asus-laptop.c
|
||||
|
||||
ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
W: http://sourceforge.net/projects/xscaleiop
|
||||
|
@ -2414,22 +2406,6 @@ T: git git://git.alsa-project.org/alsa-kernel.git
|
|||
S: Maintained
|
||||
F: sound/usb/misc/ua101.c
|
||||
|
||||
EEEPC LAPTOP EXTRAS DRIVER
|
||||
M: Corentin Chary <corentincj@iksaif.net>
|
||||
L: acpi4asus-user@lists.sourceforge.net
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
W: http://acpi4asus.sf.net
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/eeepc-laptop.c
|
||||
|
||||
EEEPC WMI EXTRAS DRIVER
|
||||
M: Corentin Chary <corentincj@iksaif.net>
|
||||
L: acpi4asus-user@lists.sourceforge.net
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
W: http://acpi4asus.sf.net
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/eeepc-wmi.c
|
||||
|
||||
EFIFB FRAMEBUFFER DRIVER
|
||||
L: linux-fbdev@vger.kernel.org
|
||||
M: Peter Jones <pjones@redhat.com>
|
||||
|
|
4
Makefile
4
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 38
|
||||
EXTRAVERSION =
|
||||
SUBLEVEL = 39
|
||||
EXTRAVERSION = -rc1
|
||||
NAME = Flesh-Eating Bats with Fangs
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -11,6 +11,7 @@ config ALPHA
|
|||
select HAVE_GENERIC_HARDIRQS
|
||||
select GENERIC_IRQ_PROBE
|
||||
select AUTO_IRQ_AFFINITY if SMP
|
||||
select GENERIC_IRQ_SHOW
|
||||
select GENERIC_HARDIRQS_NO_DEPRECATED
|
||||
help
|
||||
The Alpha is a 64-bit general-purpose processor designed and
|
||||
|
|
|
@ -67,68 +67,21 @@ int irq_select_affinity(unsigned int irq)
|
|||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
int
|
||||
show_interrupts(struct seq_file *p, void *v)
|
||||
int arch_show_interrupts(struct seq_file *p, int prec)
|
||||
{
|
||||
int j;
|
||||
int irq = *(loff_t *) v;
|
||||
struct irqaction * action;
|
||||
struct irq_desc *desc;
|
||||
unsigned long flags;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
if (irq == 0) {
|
||||
seq_puts(p, " ");
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "CPU%d ", j);
|
||||
seq_putc(p, '\n');
|
||||
}
|
||||
seq_puts(p, "IPI: ");
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
|
||||
seq_putc(p, '\n');
|
||||
#endif
|
||||
|
||||
if (irq < ACTUAL_NR_IRQS) {
|
||||
desc = irq_to_desc(irq);
|
||||
|
||||
if (!desc)
|
||||
return 0;
|
||||
|
||||
raw_spin_lock_irqsave(&desc->lock, flags);
|
||||
action = desc->action;
|
||||
if (!action)
|
||||
goto unlock;
|
||||
seq_printf(p, "%3d: ", irq);
|
||||
#ifndef CONFIG_SMP
|
||||
seq_printf(p, "%10u ", kstat_irqs(irq));
|
||||
#else
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j));
|
||||
#endif
|
||||
seq_printf(p, " %14s", get_irq_desc_chip(desc)->name);
|
||||
seq_printf(p, " %c%s",
|
||||
(action->flags & IRQF_DISABLED)?'+':' ',
|
||||
action->name);
|
||||
|
||||
for (action=action->next; action; action = action->next) {
|
||||
seq_printf(p, ", %c%s",
|
||||
(action->flags & IRQF_DISABLED)?'+':' ',
|
||||
action->name);
|
||||
}
|
||||
|
||||
seq_putc(p, '\n');
|
||||
unlock:
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
} else if (irq == ACTUAL_NR_IRQS) {
|
||||
#ifdef CONFIG_SMP
|
||||
seq_puts(p, "IPI: ");
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
|
||||
seq_putc(p, '\n');
|
||||
#endif
|
||||
seq_puts(p, "PMI: ");
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
|
||||
seq_puts(p, " Performance Monitoring\n");
|
||||
seq_printf(p, "ERR: %10lu\n", irq_err_count);
|
||||
}
|
||||
seq_puts(p, "PMI: ");
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
|
||||
seq_puts(p, " Performance Monitoring\n");
|
||||
seq_printf(p, "ERR: %10lu\n", irq_err_count);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -228,7 +228,7 @@ struct irqaction timer_irqaction = {
|
|||
void __init
|
||||
init_rtc_irq(void)
|
||||
{
|
||||
set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
|
||||
irq_set_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
|
||||
handle_simple_irq, "RTC");
|
||||
setup_irq(RTC_IRQ, &timer_irqaction);
|
||||
}
|
||||
|
|
|
@ -92,7 +92,7 @@ init_i8259a_irqs(void)
|
|||
outb(0xff, 0xA1); /* mask all of 8259A-2 */
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
|
||||
}
|
||||
|
||||
setup_irq(2, &cascade);
|
||||
|
|
|
@ -102,7 +102,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
|
|||
for (i = 16; i < 48; ++i) {
|
||||
if ((ignore_mask >> i) & 1)
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -51,7 +51,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
|
|||
for (i = 16; i < max; ++i) {
|
||||
if (i < 64 && ((ignore_mask >> i) & 1))
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &srm_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -125,7 +125,7 @@ alcor_init_irq(void)
|
|||
on while IRQ probing. */
|
||||
if (i >= 16+20 && i <= 16+30)
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
|
||||
|
|
|
@ -105,8 +105,8 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
|
|||
outb(0xff, 0x806);
|
||||
|
||||
for (i = 16; i < 35; ++i) {
|
||||
set_irq_chip_and_handler(i, &cabriolet_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &cabriolet_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -270,7 +270,7 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
|
|||
{
|
||||
long i;
|
||||
for (i = imin; i <= imax; ++i) {
|
||||
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -118,7 +118,7 @@ eb64p_init_irq(void)
|
|||
init_i8259a_irqs();
|
||||
|
||||
for (i = 16; i < 32; ++i) {
|
||||
set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -138,7 +138,7 @@ eiger_init_irq(void)
|
|||
init_i8259a_irqs();
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -171,11 +171,11 @@ jensen_init_irq(void)
|
|||
{
|
||||
init_i8259a_irqs();
|
||||
|
||||
set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
|
||||
set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
|
||||
set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
|
||||
set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
|
||||
set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
|
||||
|
||||
common_init_isa_dma();
|
||||
}
|
||||
|
|
|
@ -276,7 +276,7 @@ init_io7_irqs(struct io7 *io7,
|
|||
|
||||
/* Set up the lsi irqs. */
|
||||
for (i = 0; i < 128; ++i) {
|
||||
set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
|
||||
irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
@ -290,7 +290,7 @@ init_io7_irqs(struct io7 *io7,
|
|||
|
||||
/* Set up the msi irqs. */
|
||||
for (i = 128; i < (128 + 512); ++i) {
|
||||
set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
|
||||
irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
@ -308,8 +308,8 @@ marvel_init_irq(void)
|
|||
|
||||
/* Reserve the legacy irqs. */
|
||||
for (i = 0; i < 16; ++i) {
|
||||
set_irq_chip_and_handler(i, &marvel_legacy_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &marvel_legacy_irq_type,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
/* Init the io7 irqs. */
|
||||
|
|
|
@ -98,7 +98,8 @@ mikasa_init_irq(void)
|
|||
mikasa_update_irq_hw(0);
|
||||
|
||||
for (i = 16; i < 32; ++i) {
|
||||
set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &mikasa_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -127,7 +127,8 @@ noritake_init_irq(void)
|
|||
outw(0, 0x54c);
|
||||
|
||||
for (i = 16; i < 48; ++i) {
|
||||
set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &noritake_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -180,7 +180,8 @@ rawhide_init_irq(void)
|
|||
}
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &rawhide_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -99,7 +99,7 @@ rx164_init_irq(void)
|
|||
|
||||
rx164_update_irq_hw(0);
|
||||
for (i = 16; i < 40; ++i) {
|
||||
set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -518,8 +518,8 @@ sable_lynx_init_irq(int nr_of_irqs)
|
|||
long i;
|
||||
|
||||
for (i = 0; i < nr_of_irqs; ++i) {
|
||||
set_irq_chip_and_handler(i, &sable_lynx_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &sable_lynx_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -138,7 +138,8 @@ takara_init_irq(void)
|
|||
takara_update_irq_hw(i, -1);
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &takara_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -179,7 +179,7 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
|
|||
{
|
||||
long i;
|
||||
for (i = imin; i <= imax; ++i) {
|
||||
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -183,17 +183,17 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
|
|||
for (i = 0; i < 16; ++i) {
|
||||
if (i == 2)
|
||||
continue;
|
||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
|
||||
for (i = 40; i < 64; ++i) {
|
||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -28,6 +28,7 @@ config ARM
|
|||
select HAVE_C_RECORDMCOUNT
|
||||
select HAVE_GENERIC_HARDIRQS
|
||||
select HAVE_SPARSE_IRQ
|
||||
select GENERIC_IRQ_SHOW
|
||||
help
|
||||
The ARM series is a line of low-power-consumption RISC chip designs
|
||||
licensed by ARM Ltd and targeted at embedded applications and
|
||||
|
@ -2009,6 +2010,7 @@ menu "Power management options"
|
|||
source "kernel/power/Kconfig"
|
||||
|
||||
config ARCH_SUSPEND_POSSIBLE
|
||||
depends on !ARCH_S5P64X0 && !ARCH_S5P6442
|
||||
def_bool y
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
|
|||
|
||||
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct gic_chip_data *chip_data = get_irq_data(irq);
|
||||
struct irq_chip *chip = get_irq_chip(irq);
|
||||
struct gic_chip_data *chip_data = irq_get_handler_data(irq);
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
unsigned int cascade_irq, gic_irq;
|
||||
unsigned long status;
|
||||
|
||||
|
@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
|
|||
{
|
||||
if (gic_nr >= MAX_GIC_NR)
|
||||
BUG();
|
||||
if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
|
||||
if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
|
||||
BUG();
|
||||
set_irq_chained_handler(irq, gic_handle_cascade_irq);
|
||||
irq_set_chained_handler(irq, gic_handle_cascade_irq);
|
||||
}
|
||||
|
||||
static void __init gic_dist_init(struct gic_chip_data *gic,
|
||||
|
@ -319,9 +319,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
|
|||
* Setup the Linux IRQ subsystem.
|
||||
*/
|
||||
for (i = irq_start; i < irq_limit; i++) {
|
||||
set_irq_chip(i, &gic_chip);
|
||||
set_irq_chip_data(i, gic);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
|
||||
irq_set_chip_data(i, gic);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
|
@ -382,7 +381,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq)
|
|||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
irq_to_desc(irq)->status |= IRQ_NOPROBE;
|
||||
irq_set_status_flags(irq, IRQ_NOPROBE);
|
||||
gic_unmask_irq(irq_get_irq_data(irq));
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
|
|
@ -88,8 +88,8 @@ void it8152_init_irq(void)
|
|||
__raw_writel((0), IT8152_INTC_LDCNIRR);
|
||||
|
||||
for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
|
||||
set_irq_chip(irq, &it8152_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &it8152_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = {
|
|||
|
||||
static void locomo_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct locomo *lchip = get_irq_chip_data(irq);
|
||||
struct locomo *lchip = irq_get_chip_data(irq);
|
||||
int req, i;
|
||||
|
||||
/* Acknowledge the parent IRQ */
|
||||
|
@ -197,15 +197,14 @@ static void locomo_setup_irq(struct locomo *lchip)
|
|||
/*
|
||||
* Install handler for IRQ_LOCOMO_HW.
|
||||
*/
|
||||
set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
|
||||
set_irq_chip_data(lchip->irq, lchip);
|
||||
set_irq_chained_handler(lchip->irq, locomo_handler);
|
||||
irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
|
||||
irq_set_chip_data(lchip->irq, lchip);
|
||||
irq_set_chained_handler(lchip->irq, locomo_handler);
|
||||
|
||||
/* Install handlers for IRQ_LOCOMO_* */
|
||||
for ( ; irq <= lchip->irq_base + 3; irq++) {
|
||||
set_irq_chip(irq, &locomo_chip);
|
||||
set_irq_chip_data(irq, lchip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
|
||||
irq_set_chip_data(irq, lchip);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
@ -476,8 +475,8 @@ static void __locomo_remove(struct locomo *lchip)
|
|||
device_for_each_child(lchip->dev, NULL, locomo_remove_child);
|
||||
|
||||
if (lchip->irq != NO_IRQ) {
|
||||
set_irq_chained_handler(lchip->irq, NULL);
|
||||
set_irq_data(lchip->irq, NULL);
|
||||
irq_set_chained_handler(lchip->irq, NULL);
|
||||
irq_set_handler_data(lchip->irq, NULL);
|
||||
}
|
||||
|
||||
iounmap(lchip->base);
|
||||
|
|
|
@ -202,7 +202,7 @@ static void
|
|||
sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned int stat0, stat1, i;
|
||||
struct sa1111 *sachip = get_irq_data(irq);
|
||||
struct sa1111 *sachip = irq_get_handler_data(irq);
|
||||
void __iomem *mapbase = sachip->base + SA1111_INTC;
|
||||
|
||||
stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
|
||||
|
@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
|
|||
sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
|
||||
|
||||
for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
|
||||
set_irq_chip(irq, &sa1111_low_chip);
|
||||
set_irq_chip_data(irq, sachip);
|
||||
set_irq_handler(irq, handle_edge_irq);
|
||||
irq_set_chip_and_handler(irq, &sa1111_low_chip,
|
||||
handle_edge_irq);
|
||||
irq_set_chip_data(irq, sachip);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
|
||||
set_irq_chip(irq, &sa1111_high_chip);
|
||||
set_irq_chip_data(irq, sachip);
|
||||
set_irq_handler(irq, handle_edge_irq);
|
||||
irq_set_chip_and_handler(irq, &sa1111_high_chip,
|
||||
handle_edge_irq);
|
||||
irq_set_chip_data(irq, sachip);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Register SA1111 interrupt
|
||||
*/
|
||||
set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
|
||||
set_irq_data(sachip->irq, sachip);
|
||||
set_irq_chained_handler(sachip->irq, sa1111_irq_handler);
|
||||
irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
|
||||
irq_set_handler_data(sachip->irq, sachip);
|
||||
irq_set_chained_handler(sachip->irq, sa1111_irq_handler);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip)
|
|||
clk_disable(sachip->clk);
|
||||
|
||||
if (sachip->irq != NO_IRQ) {
|
||||
set_irq_chained_handler(sachip->irq, NULL);
|
||||
set_irq_data(sachip->irq, NULL);
|
||||
irq_set_chained_handler(sachip->irq, NULL);
|
||||
irq_set_handler_data(sachip->irq, NULL);
|
||||
|
||||
release_mem_region(sachip->phys + SA1111_INTC, 512);
|
||||
}
|
||||
|
|
|
@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base,
|
|||
if (vic_sources & (1 << i)) {
|
||||
unsigned int irq = irq_start + i;
|
||||
|
||||
set_irq_chip(irq, &vic_chip);
|
||||
set_irq_chip_data(irq, base);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &vic_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(irq, base);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -10,14 +10,6 @@ static inline void ack_bad_irq(int irq)
|
|||
irq_err_count++;
|
||||
}
|
||||
|
||||
/*
|
||||
* Obsolete inline function for calling irq descriptor handlers.
|
||||
*/
|
||||
static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
desc->handle_irq(irq, desc);
|
||||
}
|
||||
|
||||
void set_irq_flags(unsigned int irq, unsigned int flags);
|
||||
|
||||
#define IRQF_VALID (1 << 0)
|
||||
|
|
|
@ -158,31 +158,6 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
|
|||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
|
||||
|
||||
/*
|
||||
* Same as above. The PrPMC800 carrier board for the PrPMC1100
|
||||
* card maps the host-bridge @ 00:01:00 for some reason and it
|
||||
* ends up getting scanned. Note that we only want to do this
|
||||
* fixup when we find the IXP4xx on a PrPMC system, which is why
|
||||
* we check the machine type. We could be running on a board
|
||||
* with an IXP4xx target device and we don't want to kill the
|
||||
* resources in that case.
|
||||
*/
|
||||
static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (machine_is_prpmc1100()) {
|
||||
dev->class &= 0xff;
|
||||
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
|
||||
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
||||
dev->resource[i].start = 0;
|
||||
dev->resource[i].end = 0;
|
||||
dev->resource[i].flags = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100);
|
||||
|
||||
/*
|
||||
* PCI IDE controllers use non-standard I/O port decoding, respect it.
|
||||
*/
|
||||
|
|
|
@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type)
|
|||
*/
|
||||
if (slot < 8) {
|
||||
ec->irq = 32 + slot;
|
||||
set_irq_chip(ec->irq, &ecard_chip);
|
||||
set_irq_handler(ec->irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(ec->irq, &ecard_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(ec->irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
|
@ -1103,7 +1103,7 @@ static int __init ecard_init(void)
|
|||
|
||||
irqhw = ecard_probeirqhw();
|
||||
|
||||
set_irq_chained_handler(IRQ_EXPANSIONCARD,
|
||||
irq_set_chained_handler(IRQ_EXPANSIONCARD,
|
||||
irqhw ? ecard_irqexp_handler : ecard_irq_handler);
|
||||
|
||||
ecard_proc_init();
|
||||
|
|
|
@ -51,63 +51,18 @@
|
|||
|
||||
unsigned long irq_err_count;
|
||||
|
||||
int show_interrupts(struct seq_file *p, void *v)
|
||||
int arch_show_interrupts(struct seq_file *p, int prec)
|
||||
{
|
||||
int i = *(loff_t *) v, cpu;
|
||||
struct irq_desc *desc;
|
||||
struct irqaction * action;
|
||||
unsigned long flags;
|
||||
int prec, n;
|
||||
|
||||
for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++)
|
||||
n *= 10;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
if (prec < 4)
|
||||
prec = 4;
|
||||
#endif
|
||||
|
||||
if (i == 0) {
|
||||
char cpuname[12];
|
||||
|
||||
seq_printf(p, "%*s ", prec, "");
|
||||
for_each_present_cpu(cpu) {
|
||||
sprintf(cpuname, "CPU%d", cpu);
|
||||
seq_printf(p, " %10s", cpuname);
|
||||
}
|
||||
seq_putc(p, '\n');
|
||||
}
|
||||
|
||||
if (i < nr_irqs) {
|
||||
desc = irq_to_desc(i);
|
||||
raw_spin_lock_irqsave(&desc->lock, flags);
|
||||
action = desc->action;
|
||||
if (!action)
|
||||
goto unlock;
|
||||
|
||||
seq_printf(p, "%*d: ", prec, i);
|
||||
for_each_present_cpu(cpu)
|
||||
seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
|
||||
seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
|
||||
seq_printf(p, " %s", action->name);
|
||||
for (action = action->next; action; action = action->next)
|
||||
seq_printf(p, ", %s", action->name);
|
||||
|
||||
seq_putc(p, '\n');
|
||||
unlock:
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
} else if (i == nr_irqs) {
|
||||
#ifdef CONFIG_FIQ
|
||||
show_fiq_list(p, prec);
|
||||
show_fiq_list(p, prec);
|
||||
#endif
|
||||
#ifdef CONFIG_SMP
|
||||
show_ipi_list(p, prec);
|
||||
show_ipi_list(p, prec);
|
||||
#endif
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
show_local_irqs(p, prec);
|
||||
show_local_irqs(p, prec);
|
||||
#endif
|
||||
seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
|
||||
}
|
||||
seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -144,24 +99,21 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
|||
|
||||
void set_irq_flags(unsigned int irq, unsigned int iflags)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
unsigned long flags;
|
||||
unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
|
||||
if (irq >= nr_irqs) {
|
||||
printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
|
||||
return;
|
||||
}
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
raw_spin_lock_irqsave(&desc->lock, flags);
|
||||
desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
if (iflags & IRQF_VALID)
|
||||
desc->status &= ~IRQ_NOREQUEST;
|
||||
clr |= IRQ_NOREQUEST;
|
||||
if (iflags & IRQF_PROBE)
|
||||
desc->status &= ~IRQ_NOPROBE;
|
||||
clr |= IRQ_NOPROBE;
|
||||
if (!(iflags & IRQF_NOAUTOEN))
|
||||
desc->status &= ~IRQ_NOAUTOEN;
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
clr |= IRQ_NOAUTOEN;
|
||||
/* Order is clear bits in "clr" then set bits in "set" */
|
||||
irq_modify_status(irq, clr, set & ~clr);
|
||||
}
|
||||
|
||||
void __init init_IRQ(void)
|
||||
|
|
|
@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
|
|||
return;
|
||||
|
||||
if (cpu_is_at91cap9_revB())
|
||||
set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
|
||||
irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
|
||||
|
||||
/* Enable VBus control for UHP ports */
|
||||
for (i = 0; i < data->ports; i++) {
|
||||
|
@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = {
|
|||
void __init at91_add_device_usba(struct usba_platform_data *data)
|
||||
{
|
||||
if (cpu_is_at91cap9_revB()) {
|
||||
set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
|
||||
irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
|
||||
at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
|
||||
AT91_MATRIX_UDPHS_BYPASS_LOCK);
|
||||
}
|
||||
|
@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
|||
return;
|
||||
|
||||
if (cpu_is_at91cap9_revB())
|
||||
set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
|
||||
irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
|
||||
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
|
||||
|
|
|
@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
|
|||
else
|
||||
wakeups[bank] &= ~mask;
|
||||
|
||||
set_irq_wake(gpio_chip[bank].bank->id, state);
|
||||
irq_set_irq_wake(gpio_chip[bank].bank->id, state);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -375,6 +375,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
|
|||
|
||||
static struct irq_chip gpio_irqchip = {
|
||||
.name = "GPIO",
|
||||
.irq_disable = gpio_irq_mask,
|
||||
.irq_mask = gpio_irq_mask,
|
||||
.irq_unmask = gpio_irq_unmask,
|
||||
.irq_set_type = gpio_irq_type,
|
||||
|
@ -384,16 +385,14 @@ static struct irq_chip gpio_irqchip = {
|
|||
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned pin;
|
||||
struct irq_desc *gpio;
|
||||
struct at91_gpio_chip *at91_gpio;
|
||||
void __iomem *pio;
|
||||
struct irq_data *idata = irq_desc_get_irq_data(desc);
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(idata);
|
||||
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
|
||||
void __iomem *pio = at91_gpio->regbase;
|
||||
u32 isr;
|
||||
|
||||
at91_gpio = get_irq_chip_data(irq);
|
||||
pio = at91_gpio->regbase;
|
||||
|
||||
/* temporarily mask (level sensitive) parent IRQ */
|
||||
desc->irq_data.chip->irq_ack(&desc->irq_data);
|
||||
chip->irq_ack(idata);
|
||||
for (;;) {
|
||||
/* Reading ISR acks pending (edge triggered) GPIO interrupts.
|
||||
* When there none are pending, we're finished unless we need
|
||||
|
@ -409,27 +408,15 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
|
|||
}
|
||||
|
||||
pin = at91_gpio->chip.base;
|
||||
gpio = &irq_desc[pin];
|
||||
|
||||
while (isr) {
|
||||
if (isr & 1) {
|
||||
if (unlikely(gpio->depth)) {
|
||||
/*
|
||||
* The core ARM interrupt handler lazily disables IRQs so
|
||||
* another IRQ must be generated before it actually gets
|
||||
* here to be disabled on the GPIO controller.
|
||||
*/
|
||||
gpio_irq_mask(irq_get_irq_data(pin));
|
||||
}
|
||||
else
|
||||
generic_handle_irq(pin);
|
||||
}
|
||||
if (isr & 1)
|
||||
generic_handle_irq(pin);
|
||||
pin++;
|
||||
gpio++;
|
||||
isr >>= 1;
|
||||
}
|
||||
}
|
||||
desc->irq_data.chip->irq_unmask(&desc->irq_data);
|
||||
chip->irq_unmask(idata);
|
||||
/* now it may re-trigger */
|
||||
}
|
||||
|
||||
|
@ -518,14 +505,14 @@ void __init at91_gpio_irq_setup(void)
|
|||
__raw_writel(~0, this->regbase + PIO_IDR);
|
||||
|
||||
for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
|
||||
lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
|
||||
irq_set_lockdep_class(pin, &gpio_lock_class);
|
||||
|
||||
/*
|
||||
* Can use the "simple" and not "edge" handler since it's
|
||||
* shorter, and the AIC handles interrupts sanely.
|
||||
*/
|
||||
set_irq_chip(pin, &gpio_irqchip);
|
||||
set_irq_handler(pin, handle_simple_irq);
|
||||
irq_set_chip_and_handler(pin, &gpio_irqchip,
|
||||
handle_simple_irq);
|
||||
set_irq_flags(pin, IRQF_VALID);
|
||||
}
|
||||
|
||||
|
@ -536,8 +523,8 @@ void __init at91_gpio_irq_setup(void)
|
|||
if (prev && prev->next == this)
|
||||
continue;
|
||||
|
||||
set_irq_chip_data(id, this);
|
||||
set_irq_chained_handler(id, gpio_irq_handler);
|
||||
irq_set_chip_data(id, this);
|
||||
irq_set_chained_handler(id, gpio_irq_handler);
|
||||
}
|
||||
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
|
||||
}
|
||||
|
|
|
@ -89,7 +89,7 @@
|
|||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
|
|
|
@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
|
|||
/* Active Low interrupt, with the specified priority */
|
||||
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
|
||||
|
||||
set_irq_chip(i, &at91_aic_chip);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
|
||||
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
|
||||
|
|
|
@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip,
|
|||
unsigned int i;
|
||||
for (i = 0; i < 32; i++) {
|
||||
unsigned int irq = irq_start + i;
|
||||
set_irq_chip(irq, chip);
|
||||
set_irq_chip_data(irq, base);
|
||||
irq_set_chip(irq, chip);
|
||||
irq_set_chip_data(irq, base);
|
||||
|
||||
if (vic_sources & (1 << i)) {
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_handler(irq, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
@ -119,9 +119,9 @@ void __init bcmring_init_irq(void)
|
|||
|
||||
/* special cases */
|
||||
if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
|
||||
set_irq_handler(IRQ_GPIO0, handle_simple_irq);
|
||||
irq_set_handler(IRQ_GPIO0, handle_simple_irq);
|
||||
}
|
||||
if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
|
||||
set_irq_handler(IRQ_GPIO1, handle_simple_irq);
|
||||
irq_set_handler(IRQ_GPIO1, handle_simple_irq);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -112,13 +112,13 @@ void __init clps711x_init_irq(void)
|
|||
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
if (INT1_IRQS & (1 << i)) {
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
set_irq_chip(i, &int1_chip);
|
||||
irq_set_chip_and_handler(i, &int1_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
if (INT2_IRQS & (1 << i)) {
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
set_irq_chip(i, &int2_chip);
|
||||
irq_set_chip_and_handler(i, &int2_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -167,9 +167,9 @@ void __init cp_intc_init(void)
|
|||
|
||||
/* Set up genirq dispatching for cp_intc */
|
||||
for (i = 0; i < num_irq; i++) {
|
||||
set_irq_chip(i, &cp_intc_irq_chip);
|
||||
irq_set_chip(i, &cp_intc_irq_chip);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
set_irq_handler(i, handle_edge_irq);
|
||||
irq_set_handler(i, handle_edge_irq);
|
||||
}
|
||||
|
||||
/* Enable global interrupt */
|
||||
|
|
|
@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
|
|||
{
|
||||
struct davinci_gpio_regs __iomem *g;
|
||||
|
||||
g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
|
||||
g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
|
||||
|
||||
return g;
|
||||
}
|
||||
|
@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup);
|
|||
static void gpio_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
|
||||
u32 mask = (u32) irq_data_get_irq_data(d);
|
||||
u32 mask = (u32) irq_data_get_irq_handler_data(d);
|
||||
|
||||
__raw_writel(mask, &g->clr_falling);
|
||||
__raw_writel(mask, &g->clr_rising);
|
||||
|
@ -217,8 +217,8 @@ static void gpio_irq_disable(struct irq_data *d)
|
|||
static void gpio_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
|
||||
u32 mask = (u32) irq_data_get_irq_data(d);
|
||||
unsigned status = irq_desc[d->irq].status;
|
||||
u32 mask = (u32) irq_data_get_irq_handler_data(d);
|
||||
unsigned status = irqd_get_trigger_type(d);
|
||||
|
||||
status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
|
||||
if (!status)
|
||||
|
@ -233,21 +233,11 @@ static void gpio_irq_enable(struct irq_data *d)
|
|||
static int gpio_irq_type(struct irq_data *d, unsigned trigger)
|
||||
{
|
||||
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
|
||||
u32 mask = (u32) irq_data_get_irq_data(d);
|
||||
u32 mask = (u32) irq_data_get_irq_handler_data(d);
|
||||
|
||||
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
||||
return -EINVAL;
|
||||
|
||||
irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
|
||||
irq_desc[d->irq].status |= trigger;
|
||||
|
||||
/* don't enable the IRQ if it's currently disabled */
|
||||
if (irq_desc[d->irq].depth == 0) {
|
||||
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
|
||||
? &g->set_falling : &g->clr_falling);
|
||||
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
|
||||
? &g->set_rising : &g->clr_rising);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -256,6 +246,7 @@ static struct irq_chip gpio_irqchip = {
|
|||
.irq_enable = gpio_irq_enable,
|
||||
.irq_disable = gpio_irq_disable,
|
||||
.irq_set_type = gpio_irq_type,
|
||||
.flags = IRQCHIP_SET_TYPE_MASKED,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -285,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
|
|||
status >>= 16;
|
||||
|
||||
/* now demux them to the right lowlevel handler */
|
||||
n = (int)get_irq_data(irq);
|
||||
n = (int)irq_get_handler_data(irq);
|
||||
while (status) {
|
||||
res = ffs(status);
|
||||
n += res;
|
||||
|
@ -323,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
|
|||
static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
|
||||
{
|
||||
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
|
||||
u32 mask = (u32) irq_data_get_irq_data(d);
|
||||
u32 mask = (u32) irq_data_get_irq_handler_data(d);
|
||||
|
||||
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
||||
return -EINVAL;
|
||||
|
@ -395,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
|
|||
|
||||
/* AINTC handles mask/unmask; GPIO handles triggering */
|
||||
irq = bank_irq;
|
||||
gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
|
||||
gpio_irqchip_unbanked = *irq_get_chip(irq);
|
||||
gpio_irqchip_unbanked.name = "GPIO-AINTC";
|
||||
gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
|
||||
|
||||
|
@ -406,10 +397,10 @@ static int __init davinci_gpio_irq_setup(void)
|
|||
|
||||
/* set the direct IRQs up to use that irqchip */
|
||||
for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
|
||||
set_irq_chip(irq, &gpio_irqchip_unbanked);
|
||||
set_irq_data(irq, (void *) __gpio_mask(gpio));
|
||||
set_irq_chip_data(irq, (__force void *) g);
|
||||
irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
|
||||
irq_set_chip(irq, &gpio_irqchip_unbanked);
|
||||
irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
|
||||
irq_set_chip_data(irq, (__force void *)g);
|
||||
irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
|
||||
}
|
||||
|
||||
goto done;
|
||||
|
@ -430,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void)
|
|||
__raw_writel(~0, &g->clr_rising);
|
||||
|
||||
/* set up all irqs in this bank */
|
||||
set_irq_chained_handler(bank_irq, gpio_irq_handler);
|
||||
set_irq_chip_data(bank_irq, (__force void *) g);
|
||||
set_irq_data(bank_irq, (void *) irq);
|
||||
irq_set_chained_handler(bank_irq, gpio_irq_handler);
|
||||
irq_set_chip_data(bank_irq, (__force void *)g);
|
||||
irq_set_handler_data(bank_irq, (void *)irq);
|
||||
|
||||
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
|
||||
set_irq_chip(irq, &gpio_irqchip);
|
||||
set_irq_chip_data(irq, (__force void *) g);
|
||||
set_irq_data(irq, (void *) __gpio_mask(gpio));
|
||||
set_irq_handler(irq, handle_simple_irq);
|
||||
irq_set_chip(irq, &gpio_irqchip);
|
||||
irq_set_chip_data(irq, (__force void *)g);
|
||||
irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
|
||||
irq_set_handler(irq, handle_simple_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
|
|
|
@ -154,11 +154,11 @@ void __init davinci_irq_init(void)
|
|||
|
||||
/* set up genirq dispatch for ARM INTC */
|
||||
for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
|
||||
set_irq_chip(i, &davinci_irq_chip_0);
|
||||
irq_set_chip(i, &davinci_irq_chip_0);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
if (i != IRQ_TINT1_TINT34)
|
||||
set_irq_handler(i, handle_edge_irq);
|
||||
irq_set_handler(i, handle_edge_irq);
|
||||
else
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_handler(i, handle_level_irq);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -136,7 +136,7 @@
|
|||
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
|
||||
#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
|
||||
#define DOVE_NAND_GPIO_EN (1 << 0)
|
||||
#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40)
|
||||
#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
|
||||
#define DOVE_SPI_GPIO_SEL (1 << 5)
|
||||
#define DOVE_UART1_GPIO_SEL (1 << 4)
|
||||
#define DOVE_AU1_GPIO_SEL (1 << 3)
|
||||
|
|
|
@ -86,8 +86,7 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|||
if (!(cause & (1 << irq)))
|
||||
continue;
|
||||
irq = pmu_to_irq(irq);
|
||||
desc = irq_desc + irq;
|
||||
desc_handle_irq(irq, desc);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -103,14 +102,14 @@ void __init dove_init_irq(void)
|
|||
*/
|
||||
orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
|
||||
IRQ_DOVE_GPIO_START);
|
||||
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
|
||||
|
||||
orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
|
||||
IRQ_DOVE_GPIO_START + 32);
|
||||
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
|
||||
|
||||
orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
|
||||
IRQ_DOVE_GPIO_START + 64);
|
||||
|
@ -122,10 +121,9 @@ void __init dove_init_irq(void)
|
|||
writel(0, PMU_INTERRUPT_CAUSE);
|
||||
|
||||
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
|
||||
set_irq_chip(i, &pmu_irq_chip);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_desc[i].status |= IRQ_LEVEL;
|
||||
irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
}
|
||||
set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
|
||||
irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
|
||||
}
|
||||
|
|
|
@ -147,9 +147,6 @@ void __init dove_mpp_conf(unsigned int *mpp_list)
|
|||
u32 pmu_sig_ctrl[PMU_SIG_REGS];
|
||||
int i;
|
||||
|
||||
/* Initialize gpiolib. */
|
||||
orion_gpio_init();
|
||||
|
||||
for (i = 0; i < MPP_NR_REGS; i++)
|
||||
mpp_ctrl[i] = readl(MPP_CTRL(i));
|
||||
|
||||
|
|
|
@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void)
|
|||
local_irq_restore(flags);
|
||||
|
||||
for (irq = 0; irq < NR_IRQS; irq++) {
|
||||
set_irq_chip(irq, &ebsa110_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -117,7 +117,7 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d)
|
|||
int port = line >> 3;
|
||||
int port_mask = 1 << (line & 7);
|
||||
|
||||
if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
|
||||
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
|
||||
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
|
||||
ep93xx_gpio_update_int_params(port);
|
||||
}
|
||||
|
@ -131,7 +131,7 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
|
|||
int port = line >> 3;
|
||||
int port_mask = 1 << (line & 7);
|
||||
|
||||
if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
||||
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
|
||||
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
|
||||
|
||||
gpio_int_unmasked[port] &= ~port_mask;
|
||||
|
@ -165,10 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d)
|
|||
*/
|
||||
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct irq_desc *desc = irq_desc + d->irq;
|
||||
const int gpio = irq_to_gpio(d->irq);
|
||||
const int port = gpio >> 3;
|
||||
const int port_mask = 1 << (gpio & 7);
|
||||
irq_flow_handler_t handler;
|
||||
|
||||
gpio_direction_input(gpio);
|
||||
|
||||
|
@ -176,22 +176,22 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
|
|||
case IRQ_TYPE_EDGE_RISING:
|
||||
gpio_int_type1[port] |= port_mask;
|
||||
gpio_int_type2[port] |= port_mask;
|
||||
desc->handle_irq = handle_edge_irq;
|
||||
handler = handle_edge_irq;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
gpio_int_type1[port] |= port_mask;
|
||||
gpio_int_type2[port] &= ~port_mask;
|
||||
desc->handle_irq = handle_edge_irq;
|
||||
handler = handle_edge_irq;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
gpio_int_type1[port] &= ~port_mask;
|
||||
gpio_int_type2[port] |= port_mask;
|
||||
desc->handle_irq = handle_level_irq;
|
||||
handler = handle_level_irq;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
gpio_int_type1[port] &= ~port_mask;
|
||||
gpio_int_type2[port] &= ~port_mask;
|
||||
desc->handle_irq = handle_level_irq;
|
||||
handler = handle_level_irq;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
gpio_int_type1[port] |= port_mask;
|
||||
|
@ -200,17 +200,16 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
|
|||
gpio_int_type2[port] &= ~port_mask; /* falling */
|
||||
else
|
||||
gpio_int_type2[port] |= port_mask; /* rising */
|
||||
desc->handle_irq = handle_edge_irq;
|
||||
handler = handle_edge_irq;
|
||||
break;
|
||||
default:
|
||||
pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpio_int_enabled[port] |= port_mask;
|
||||
__irq_set_handler_locked(d->irq, handler);
|
||||
|
||||
desc->status &= ~IRQ_TYPE_SENSE_MASK;
|
||||
desc->status |= type & IRQ_TYPE_SENSE_MASK;
|
||||
gpio_int_enabled[port] |= port_mask;
|
||||
|
||||
ep93xx_gpio_update_int_params(port);
|
||||
|
||||
|
@ -232,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void)
|
|||
|
||||
for (gpio_irq = gpio_to_irq(0);
|
||||
gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
|
||||
set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
|
||||
set_irq_handler(gpio_irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(gpio_irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
|
||||
set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
|
||||
ep93xx_gpio_ab_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
|
||||
ep93xx_gpio_f_irq_handler);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -20,6 +20,11 @@ config EXYNOS4_MCT
|
|||
help
|
||||
Use MCT (Multi Core Timer) as kernel timers
|
||||
|
||||
config EXYNOS4_DEV_AHCI
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for AHCI
|
||||
|
||||
config EXYNOS4_DEV_PD
|
||||
bool
|
||||
help
|
||||
|
@ -134,9 +139,9 @@ config MACH_ARMLEX4210
|
|||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select EXYNOS4_DEV_AHCI
|
||||
select EXYNOS4_DEV_SYSMMU
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select SATA_AHCI_PLATFORM
|
||||
help
|
||||
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
|
||||
|
||||
|
|
|
@ -39,6 +39,7 @@ obj-$(CONFIG_MACH_NURI) += mach-nuri.o
|
|||
# device support
|
||||
|
||||
obj-y += dev-audio.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
|
||||
|
||||
|
@ -53,4 +54,3 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
|
|||
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
|
||||
obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o
|
||||
|
|
|
@ -21,8 +21,8 @@
|
|||
*/
|
||||
|
||||
.macro addruart, rp, rv
|
||||
ldreq \rp, = S3C_PA_UART
|
||||
ldrne \rv, = S3C_VA_UART
|
||||
ldr \rp, = S3C_PA_UART
|
||||
ldr \rv, = S3C_VA_UART
|
||||
#if CONFIG_DEBUG_S3C_UART != 0
|
||||
add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
|
||||
add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
|
||||
|
|
|
@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data)
|
|||
|
||||
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct combiner_chip_data *chip_data = get_irq_data(irq);
|
||||
struct irq_chip *chip = get_irq_chip(irq);
|
||||
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
unsigned int cascade_irq, combiner_irq;
|
||||
unsigned long status;
|
||||
|
||||
|
@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
|
|||
{
|
||||
if (combiner_nr >= MAX_COMBINER_NR)
|
||||
BUG();
|
||||
if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
|
||||
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
|
||||
BUG();
|
||||
set_irq_chained_handler(irq, combiner_handle_cascade_irq);
|
||||
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
|
||||
}
|
||||
|
||||
void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
|
||||
|
@ -119,9 +119,8 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
|
|||
|
||||
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
|
||||
+ MAX_IRQ_IN_COMBINER; i++) {
|
||||
set_irq_chip(i, &combiner_chip);
|
||||
set_irq_chip_data(i, &combiner_data[combiner_nr]);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
|
||||
irq_set_chip_data(i, &combiner_data[combiner_nr]);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
|
|||
|
||||
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 *irq_data = get_irq_data(irq);
|
||||
struct irq_chip *chip = get_irq_chip(irq);
|
||||
u32 *irq_data = irq_get_handler_data(irq);
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
|
||||
chip->irq_mask(&desc->irq_data);
|
||||
|
||||
|
@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void)
|
|||
int irq;
|
||||
|
||||
for (irq = 0 ; irq <= 31 ; irq++) {
|
||||
set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
|
||||
set_irq_handler(IRQ_EINT(irq), handle_level_irq);
|
||||
irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
|
||||
handle_level_irq);
|
||||
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
|
||||
}
|
||||
|
||||
set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
|
||||
irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
|
||||
|
||||
for (irq = 0 ; irq <= 15 ; irq++) {
|
||||
eint0_15_data[irq] = IRQ_EINT(irq);
|
||||
|
||||
set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
|
||||
set_irq_chained_handler(exynos4_get_irq_nr(irq),
|
||||
irq_set_handler_data(exynos4_get_irq_nr(irq),
|
||||
&eint0_15_data[irq]);
|
||||
irq_set_chained_handler(exynos4_get_irq_nr(irq),
|
||||
exynos4_irq_eint0_15);
|
||||
}
|
||||
|
||||
|
|
|
@ -125,7 +125,7 @@ static struct resource smdkc210_smsc911x_resources[] = {
|
|||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc9215_config = {
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
|
|
|
@ -127,7 +127,7 @@ static struct resource smdkv310_smsc911x_resources[] = {
|
|||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc9215_config = {
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
|
|
|
@ -102,8 +102,7 @@ static void __init __fb_init_irq(void)
|
|||
*CSR_FIQ_DISABLE = -1;
|
||||
|
||||
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
|
||||
set_irq_chip(irq, &fb_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -30,7 +30,7 @@ static int cksrc_dc21285_enable(struct clocksource *cs)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cksrc_dc21285_disable(struct clocksource *cs)
|
||||
static void cksrc_dc21285_disable(struct clocksource *cs)
|
||||
{
|
||||
*CSR_TIMER2_CNTL = 0;
|
||||
}
|
||||
|
|
|
@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq)
|
|||
|
||||
if (host_irq != (unsigned int)-1) {
|
||||
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
|
||||
set_irq_chip(irq, &isa_lo_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &isa_lo_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
|
||||
set_irq_chip(irq, &isa_hi_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &isa_hi_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
|
@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq)
|
|||
request_resource(&ioport_resource, &pic2_resource);
|
||||
setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
|
||||
|
||||
set_irq_chained_handler(host_irq, isa_irq_handler);
|
||||
irq_set_chained_handler(host_irq, isa_irq_handler);
|
||||
|
||||
/*
|
||||
* On the NetWinder, don't automatically
|
||||
|
|
|
@ -127,8 +127,8 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
|
|||
|
||||
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
|
||||
unsigned int gpio_irq_no, irq_stat;
|
||||
unsigned int port = (unsigned int)get_irq_data(irq);
|
||||
|
||||
irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
|
||||
|
||||
|
@ -138,9 +138,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|||
if ((irq_stat & 1) == 0)
|
||||
continue;
|
||||
|
||||
BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
|
||||
irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
|
||||
&irq_desc[gpio_irq_no]);
|
||||
generic_handle_irq(gpio_irq_no);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -219,13 +217,13 @@ void __init gemini_gpio_init(void)
|
|||
|
||||
for (j = GPIO_IRQ_BASE + i * 32;
|
||||
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
|
||||
set_irq_chip(j, &gpio_irq_chip);
|
||||
set_irq_handler(j, handle_edge_irq);
|
||||
irq_set_chip_and_handler(j, &gpio_irq_chip,
|
||||
handle_edge_irq);
|
||||
set_irq_flags(j, IRQF_VALID);
|
||||
}
|
||||
|
||||
set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
|
||||
set_irq_data(IRQ_GPIO(i), (void *)i);
|
||||
irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
|
||||
irq_set_handler_data(IRQ_GPIO(i), (void *)i);
|
||||
}
|
||||
|
||||
BUG_ON(gpiochip_add(&gemini_gpio_chip));
|
||||
|
|
|
@ -81,13 +81,13 @@ void __init gemini_init_irq(void)
|
|||
request_resource(&iomem_resource, &irq_resource);
|
||||
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
set_irq_chip(i, &gemini_irq_chip);
|
||||
irq_set_chip(i, &gemini_irq_chip);
|
||||
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
|
||||
set_irq_handler(i, handle_edge_irq);
|
||||
irq_set_handler(i, handle_edge_irq);
|
||||
mode |= 1 << i;
|
||||
level |= 1 << i;
|
||||
} else {
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_handler(i, handle_level_irq);
|
||||
}
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
|
|
@ -199,29 +199,29 @@ void __init h720x_init_irq (void)
|
|||
|
||||
/* Initialize global IRQ's, fast path */
|
||||
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
|
||||
set_irq_chip(irq, &h720x_global_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &h720x_global_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
/* Initialize multiplexed IRQ's, slow path */
|
||||
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
|
||||
set_irq_chip(irq, &h720x_gpio_chip);
|
||||
set_irq_handler(irq, handle_edge_irq);
|
||||
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
|
||||
handle_edge_irq);
|
||||
set_irq_flags(irq, IRQF_VALID );
|
||||
}
|
||||
set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
|
||||
set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
|
||||
set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
|
||||
set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
|
||||
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
|
||||
irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
|
||||
irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
|
||||
irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
|
||||
|
||||
#ifdef CONFIG_CPU_H7202
|
||||
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
|
||||
set_irq_chip(irq, &h720x_gpio_chip);
|
||||
set_irq_handler(irq, handle_edge_irq);
|
||||
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
|
||||
handle_edge_irq);
|
||||
set_irq_flags(irq, IRQF_VALID );
|
||||
}
|
||||
set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
|
||||
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
|
||||
#endif
|
||||
|
||||
/* Enable multiplexed irq's */
|
||||
|
|
|
@ -141,13 +141,18 @@ h7202_timer_interrupt(int irq, void *dev_id)
|
|||
/*
|
||||
* mask multiplexed timer IRQs
|
||||
*/
|
||||
static void inline mask_timerx_irq(struct irq_data *d)
|
||||
static void inline __mask_timerx_irq(unsigned int irq)
|
||||
{
|
||||
unsigned int bit;
|
||||
bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
|
||||
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
|
||||
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
|
||||
}
|
||||
|
||||
static void inline mask_timerx_irq(struct irq_data *d)
|
||||
{
|
||||
__mask_timerx_irq(d->irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* unmask multiplexed timer IRQs
|
||||
*/
|
||||
|
@ -196,12 +201,12 @@ void __init h7202_init_irq (void)
|
|||
|
||||
for (irq = IRQ_TIMER1;
|
||||
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
|
||||
mask_timerx_irq(irq);
|
||||
set_irq_chip(irq, &h7202_timerx_chip);
|
||||
set_irq_handler(irq, handle_edge_irq);
|
||||
__mask_timerx_irq(irq);
|
||||
irq_set_chip_and_handler(irq, &h7202_timerx_chip,
|
||||
handle_edge_irq);
|
||||
set_irq_flags(irq, IRQF_VALID );
|
||||
}
|
||||
set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
|
||||
irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
|
||||
|
||||
h720x_init_irq();
|
||||
}
|
||||
|
|
|
@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void)
|
|||
|
||||
for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
|
||||
if (i < 32)
|
||||
set_irq_chip(i, &iop13xx_irqchip1);
|
||||
irq_set_chip(i, &iop13xx_irqchip1);
|
||||
else if (i < 64)
|
||||
set_irq_chip(i, &iop13xx_irqchip2);
|
||||
irq_set_chip(i, &iop13xx_irqchip2);
|
||||
else if (i < 96)
|
||||
set_irq_chip(i, &iop13xx_irqchip3);
|
||||
irq_set_chip(i, &iop13xx_irqchip3);
|
||||
else
|
||||
set_irq_chip(i, &iop13xx_irqchip4);
|
||||
irq_set_chip(i, &iop13xx_irqchip4);
|
||||
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_handler(i, handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
|
|
|
@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
|
|||
|
||||
void __init iop13xx_msi_init(void)
|
||||
{
|
||||
set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
|
||||
irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
|
|||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
set_irq_msi(irq, desc);
|
||||
irq_set_msi_desc(irq, desc);
|
||||
|
||||
msg.address_hi = 0x0;
|
||||
msg.address_lo = IOP13XX_MU_MIMR_PCI;
|
||||
|
@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
|
|||
msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
|
||||
|
||||
write_msi_msg(irq, &msg);
|
||||
set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
|
||||
irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -68,8 +68,7 @@ void __init iop32x_init_irq(void)
|
|||
*IOP3XX_PCIIRSR = 0x0f;
|
||||
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
set_irq_chip(i, &ext_chip);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -110,8 +110,9 @@ void __init iop33x_init_irq(void)
|
|||
*IOP3XX_PCIIRSR = 0x0f;
|
||||
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_chip_and_handler(i,
|
||||
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void)
|
|||
*/
|
||||
for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
|
||||
if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
|
||||
set_irq_chip(irq, &ixp2000_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
} else set_irq_flags(irq, 0);
|
||||
}
|
||||
|
@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void)
|
|||
for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
|
||||
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
|
||||
IXP2000_VALID_ERR_IRQ_MASK) {
|
||||
set_irq_chip(irq, &ixp2000_err_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
else
|
||||
set_irq_flags(irq, 0);
|
||||
}
|
||||
set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
|
||||
irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
|
||||
|
||||
for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
|
||||
set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
|
||||
irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
|
||||
|
||||
/*
|
||||
* Enable PCI irqs. The actual PCI[AB] decoding is done in
|
||||
|
@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void)
|
|||
*/
|
||||
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
|
||||
for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
|
||||
set_irq_chip(irq, &ixp2000_pci_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
|
|||
*board_irq_mask = 0xffffffff;
|
||||
|
||||
for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
|
||||
set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
/* Hook into PCI interrupt */
|
||||
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
|
||||
irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
|
|
|
@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void)
|
|||
|
||||
for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
|
||||
if (irq & valid_irq_mask) {
|
||||
set_irq_chip(irq, &ixdp2x01_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
} else {
|
||||
set_irq_flags(irq, 0);
|
||||
|
@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void)
|
|||
}
|
||||
|
||||
/* Hook into PCI interrupts */
|
||||
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
|
||||
irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
|
|||
{
|
||||
switch (type) {
|
||||
case IXP23XX_IRQ_LEVEL:
|
||||
set_irq_chip(irq, &ixp23xx_irq_level_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
|
||||
handle_level_irq);
|
||||
break;
|
||||
case IXP23XX_IRQ_EDGE:
|
||||
set_irq_chip(irq, &ixp23xx_irq_edge_chip);
|
||||
set_irq_handler(irq, handle_edge_irq);
|
||||
irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
|
||||
handle_edge_irq);
|
||||
break;
|
||||
}
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
|
@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void)
|
|||
}
|
||||
|
||||
for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
|
||||
set_irq_chip(irq, &ixp23xx_pci_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
|
||||
irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void)
|
|||
irq++) {
|
||||
if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
set_irq_chip(irq, &ixdp2351_inta_chip);
|
||||
irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void)
|
|||
irq++) {
|
||||
if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
set_irq_chip(irq, &ixdp2351_intb_chip);
|
||||
irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
}
|
||||
|
||||
set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
|
||||
set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
|
||||
irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
|
||||
irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
|
|||
|
||||
static void __init roadrunner_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
ixp23xx_pci_preinit();
|
||||
}
|
||||
|
|
|
@ -39,10 +39,10 @@
|
|||
|
||||
void __init avila_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void)
|
|||
|
||||
/* Default to all level triggered */
|
||||
for(i = 0; i < NR_IRQS; i++) {
|
||||
set_irq_chip(i, &ixp4xx_irq_chip);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -32,8 +32,8 @@
|
|||
|
||||
void __init coyote_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -35,12 +35,12 @@
|
|||
|
||||
void __init dsmg600_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -32,9 +32,9 @@
|
|||
|
||||
void __init fsg_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -29,8 +29,8 @@
|
|||
|
||||
void __init gateway7001_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
|
|
@ -420,8 +420,8 @@ static void __init gmlr_init(void)
|
|||
gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
|
||||
gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
|
||||
gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
|
||||
|
||||
set_control(CONTROL_HSS0_DTR_N, 1);
|
||||
set_control(CONTROL_HSS1_DTR_N, 1);
|
||||
|
@ -441,10 +441,10 @@ static void __init gmlr_init(void)
|
|||
#ifdef CONFIG_PCI
|
||||
static void __init gmlr_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -43,8 +43,8 @@
|
|||
*/
|
||||
void __init gtwx5715_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -36,10 +36,10 @@
|
|||
|
||||
void __init ixdp425_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -25,8 +25,8 @@
|
|||
|
||||
void __init ixdpg425_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
|
|
@ -33,11 +33,11 @@
|
|||
|
||||
void __init nas100d_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -32,9 +32,9 @@
|
|||
|
||||
void __init nslu2_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void)
|
|||
pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
|
||||
(int)(pci_cardbus_mem_size >> 20));
|
||||
#endif
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
||||
|
|
|
@ -29,8 +29,8 @@
|
|||
|
||||
void __init wg302v2_pci_preinit(void)
|
||||
{
|
||||
set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
ixp4xx_pci_preinit();
|
||||
}
|
||||
|
|
|
@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void)
|
|||
*/
|
||||
orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
|
||||
IRQ_KIRKWOOD_GPIO_START);
|
||||
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
|
||||
|
||||
orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
|
||||
IRQ_KIRKWOOD_GPIO_START + 32);
|
||||
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
|
||||
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
|
||||
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23,
|
||||
gpio_irq_handler);
|
||||
}
|
||||
|
|
|
@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
|
|||
local_irq_restore(flags);
|
||||
|
||||
/* Set IRQ triggering type */
|
||||
set_irq_type(gpio_irq[pin], type);
|
||||
irq_set_irq_type(gpio_irq[pin], type);
|
||||
|
||||
/* enable interrupt mode */
|
||||
ks8695_gpio_mode(pin, 0);
|
||||
|
|
|
@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
}
|
||||
|
||||
if (level_triggered) {
|
||||
set_irq_chip(d->irq, &ks8695_irq_level_chip);
|
||||
set_irq_handler(d->irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
else {
|
||||
set_irq_chip(d->irq, &ks8695_irq_edge_chip);
|
||||
set_irq_handler(d->irq, handle_edge_irq);
|
||||
irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
|
||||
handle_edge_irq);
|
||||
}
|
||||
|
||||
__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
|
||||
|
@ -158,16 +158,18 @@ void __init ks8695_init_irq(void)
|
|||
case KS8695_IRQ_UART_RX:
|
||||
case KS8695_IRQ_COMM_TX:
|
||||
case KS8695_IRQ_COMM_RX:
|
||||
set_irq_chip(irq, &ks8695_irq_level_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq,
|
||||
&ks8695_irq_level_chip,
|
||||
handle_level_irq);
|
||||
break;
|
||||
|
||||
/* Edge-triggered interrupts */
|
||||
default:
|
||||
/* clear pending bit */
|
||||
ks8695_irq_ack(irq_get_irq_data(irq));
|
||||
set_irq_chip(irq, &ks8695_irq_edge_chip);
|
||||
set_irq_handler(irq, handle_edge_irq);
|
||||
irq_set_chip_and_handler(irq,
|
||||
&ks8695_irq_edge_chip,
|
||||
handle_edge_irq);
|
||||
}
|
||||
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
|
|
|
@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
|
|||
}
|
||||
|
||||
/* Ok to use the level handler for all types */
|
||||
set_irq_handler(d->irq, handle_level_irq);
|
||||
irq_set_handler(d->irq, handle_level_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void)
|
|||
|
||||
/* Configure supported IRQ's */
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
set_irq_chip(i, &lpc32xx_irq_chip);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
}
|
||||
|
||||
|
@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void)
|
|||
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
|
||||
|
||||
/* MIC SUBIRQx interrupts will route handling to the chain handlers */
|
||||
set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
|
||||
set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
|
||||
irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
|
||||
irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
|
||||
|
||||
/* Initially disable all wake events */
|
||||
__raw_writel(0, LPC32XX_CLKPWR_P01_ER);
|
||||
|
|
|
@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
|
|||
if (chip->irq_ack)
|
||||
chip->irq_ack(d);
|
||||
|
||||
set_irq_chip(irq, chip);
|
||||
irq_set_chip(irq, chip);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_handler(irq, handle_level_irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -122,7 +122,7 @@ void __init mmp2_init_icu(void)
|
|||
|
||||
for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
|
||||
icu_mask_irq(irq_get_irq_data(irq));
|
||||
set_irq_chip(irq, &icu_irq_chip);
|
||||
irq_set_chip(irq, &icu_irq_chip);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
|
||||
switch (irq) {
|
||||
|
@ -133,7 +133,7 @@ void __init mmp2_init_icu(void)
|
|||
case IRQ_MMP2_SSP_MUX:
|
||||
break;
|
||||
default:
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_handler(irq, handle_level_irq);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -149,9 +149,9 @@ void __init mmp2_init_icu(void)
|
|||
init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
|
||||
init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
|
||||
|
||||
set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
|
||||
set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
|
||||
set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
|
||||
set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
|
||||
set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
|
||||
irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
|
||||
irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
|
||||
irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
|
||||
irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
|
||||
irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
|
||||
}
|
||||
|
|
|
@ -48,8 +48,7 @@ void __init icu_init_irq(void)
|
|||
|
||||
for (irq = 0; irq < 64; irq++) {
|
||||
icu_mask_irq(irq_get_irq_data(irq));
|
||||
set_irq_chip(irq, &icu_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void)
|
|||
*/
|
||||
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
|
||||
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
|
||||
set_irq_handler(i, handle_percpu_irq);
|
||||
irq_set_handler(i, handle_percpu_irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void)
|
|||
*/
|
||||
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
|
||||
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
|
||||
set_irq_handler(i, handle_percpu_irq);
|
||||
irq_set_handler(i, handle_percpu_irq);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -214,17 +214,17 @@ int __init trout_init_gpio(void)
|
|||
{
|
||||
int i;
|
||||
for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
|
||||
set_irq_chip(i, &trout_gpio_irq_chip);
|
||||
set_irq_handler(i, handle_edge_irq);
|
||||
irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
|
||||
handle_edge_irq);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
|
||||
gpiochip_add(&msm_gpio_banks[i].chip);
|
||||
|
||||
set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
|
||||
set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
|
||||
set_irq_wake(MSM_GPIO_TO_INT(17), 1);
|
||||
irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
|
||||
irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
|
||||
irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev)
|
|||
if (IS_ERR(vreg_sdslot))
|
||||
return PTR_ERR(vreg_sdslot);
|
||||
|
||||
set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
|
||||
irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
|
||||
|
||||
if (!opt_disable_sdcard)
|
||||
msm_add_sdcc(2, &trout_sdslot_data,
|
||||
|
|
|
@ -230,18 +230,18 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio)
|
|||
val, val2);
|
||||
}
|
||||
|
||||
static void msm_gpio_irq_ack(unsigned int irq)
|
||||
static void msm_gpio_irq_ack(struct irq_data *d)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
|
||||
|
||||
writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
|
||||
if (test_bit(gpio, msm_gpio.dual_edge_irqs))
|
||||
msm_gpio_update_dual_edge_pos(gpio);
|
||||
}
|
||||
|
||||
static void msm_gpio_irq_mask(unsigned int irq)
|
||||
static void msm_gpio_irq_mask(struct irq_data *d)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
|
||||
unsigned long irq_flags;
|
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags);
|
||||
|
@ -251,9 +251,9 @@ static void msm_gpio_irq_mask(unsigned int irq)
|
|||
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
|
||||
}
|
||||
|
||||
static void msm_gpio_irq_unmask(unsigned int irq)
|
||||
static void msm_gpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
|
||||
unsigned long irq_flags;
|
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags);
|
||||
|
@ -263,9 +263,9 @@ static void msm_gpio_irq_unmask(unsigned int irq)
|
|||
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
|
||||
}
|
||||
|
||||
static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
|
||||
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
|
||||
unsigned long irq_flags;
|
||||
uint32_t bits;
|
||||
|
||||
|
@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
|
|||
|
||||
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
|
||||
bits |= BIT(INTR_DECT_CTL);
|
||||
irq_desc[irq].handle_irq = handle_edge_irq;
|
||||
__irq_set_handler_locked(d->irq, handle_edge_irq);
|
||||
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
|
||||
__set_bit(gpio, msm_gpio.dual_edge_irqs);
|
||||
else
|
||||
__clear_bit(gpio, msm_gpio.dual_edge_irqs);
|
||||
} else {
|
||||
bits &= ~BIT(INTR_DECT_CTL);
|
||||
irq_desc[irq].handle_irq = handle_level_irq;
|
||||
__irq_set_handler_locked(d->irq, handle_level_irq);
|
||||
__clear_bit(gpio, msm_gpio.dual_edge_irqs);
|
||||
}
|
||||
|
||||
|
@ -309,6 +309,7 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
|
|||
*/
|
||||
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *data = irq_desc_get_irq_data(desc);
|
||||
unsigned long i;
|
||||
|
||||
for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
|
||||
|
@ -318,21 +319,21 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|||
generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
|
||||
i));
|
||||
}
|
||||
desc->chip->ack(irq);
|
||||
data->chip->irq_ack(data);
|
||||
}
|
||||
|
||||
static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
|
||||
static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
|
||||
{
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
|
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
|
||||
|
||||
if (on) {
|
||||
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
|
||||
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
|
||||
irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
|
||||
set_bit(gpio, msm_gpio.wake_irqs);
|
||||
} else {
|
||||
clear_bit(gpio, msm_gpio.wake_irqs);
|
||||
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
|
||||
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
|
||||
irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -340,11 +341,11 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
|
|||
|
||||
static struct irq_chip msm_gpio_irq_chip = {
|
||||
.name = "msmgpio",
|
||||
.mask = msm_gpio_irq_mask,
|
||||
.unmask = msm_gpio_irq_unmask,
|
||||
.ack = msm_gpio_irq_ack,
|
||||
.set_type = msm_gpio_irq_set_type,
|
||||
.set_wake = msm_gpio_irq_set_wake,
|
||||
.irq_mask = msm_gpio_irq_mask,
|
||||
.irq_unmask = msm_gpio_irq_unmask,
|
||||
.irq_ack = msm_gpio_irq_ack,
|
||||
.irq_set_type = msm_gpio_irq_set_type,
|
||||
.irq_set_wake = msm_gpio_irq_set_wake,
|
||||
};
|
||||
|
||||
static int __devinit msm_gpio_probe(struct platform_device *dev)
|
||||
|
@ -361,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
|
|||
|
||||
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
|
||||
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
|
||||
set_irq_chip(irq, &msm_gpio_irq_chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
|
||||
irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
|
||||
msm_summary_irq_handler);
|
||||
return 0;
|
||||
}
|
||||
|
@ -378,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
|
||||
irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue