MLK-14851: ASoC: wm8962: fix clock issue for S20_3LE (part 1)
There is error log "wm8962 3-001a: Unsupported BCLK ratio 6" When the bitstream's format is S20_3LE. The reason is that the pll output is samplerate*256, which can't divide to clock samplerate*20*2. So in this patch change the pll output to samplerate*384, and use the physical_width for S20_3LE to calculate the bclk. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> [ Aisheng: split card changes ] Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>5.4-rM2-2.2.x-imx-squashed
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@ -3,6 +3,7 @@
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* wm8962.c -- WM8962 ALSA SoC Audio driver
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*
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* Copyright 2010-2 Wolfson Microelectronics plc
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* Copyright 2017 NXP
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*
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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*/
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@ -2557,11 +2558,17 @@ static int wm8962_hw_params(struct snd_pcm_substream *substream,
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{
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struct snd_soc_component *component = dai->component;
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struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
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snd_pcm_format_t sample_format = params_format(params);
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int i;
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int aif0 = 0;
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int adctl3 = 0;
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wm8962->bclk = snd_soc_params_to_bclk(params);
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if (sample_format == SNDRV_PCM_FORMAT_S20_3LE)
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wm8962->bclk = params_rate(params) *
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params_channels(params) *
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params_physical_width(params);
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else
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wm8962->bclk = snd_soc_params_to_bclk(params);
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if (params_channels(params) == 1)
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wm8962->bclk *= 2;
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