Merge branches 'fsldma' and 'intel-mid' into dmaengine
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commit
0a4bbddde2
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@ -1,7 +1,7 @@
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/*
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* Freescale MPC85xx, MPC83xx DMA Engine support
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*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author:
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* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
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@ -1322,6 +1322,8 @@ static int __devinit fsldma_of_probe(struct platform_device *op,
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fdev->common.device_control = fsl_dma_device_control;
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fdev->common.dev = &op->dev;
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dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
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dev_set_drvdata(&op->dev, fdev);
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/*
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@ -664,11 +664,20 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
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/*calculate CTL_LO*/
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ctl_lo.ctl_lo = 0;
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ctl_lo.ctlx.int_en = 1;
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ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width;
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ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width;
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ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;
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ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;
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/*
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* Here we need some translation from "enum dma_slave_buswidth"
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* to the format for our dma controller
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* standard intel_mid_dmac's format
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* 1 Byte 0b000
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* 2 Bytes 0b001
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* 4 Bytes 0b010
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*/
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ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width / 2;
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ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width / 2;
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if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
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ctl_lo.ctlx.tt_fc = 0;
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ctl_lo.ctlx.sinc = 0;
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@ -746,8 +755,18 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
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BUG_ON(!mids);
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if (!midc->dma->pimr_mask) {
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pr_debug("MDMA: SG list is not supported by this controller\n");
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return NULL;
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/* We can still handle sg list with only one item */
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if (sg_len == 1) {
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txd = intel_mid_dma_prep_memcpy(chan,
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mids->dma_slave.dst_addr,
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mids->dma_slave.src_addr,
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sgl->length,
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flags);
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return txd;
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} else {
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pr_warn("MDMA: SG list is not supported by this controller\n");
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return NULL;
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}
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}
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pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
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@ -758,6 +777,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
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pr_err("MDMA: Prep memcpy failed\n");
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return NULL;
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}
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desc = to_intel_mid_dma_desc(txd);
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desc->dirn = direction;
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ctl_lo.ctl_lo = desc->ctl_lo;
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@ -1021,11 +1041,6 @@ static irqreturn_t intel_mid_dma_interrupt(int irq, void *data)
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/*DMA Interrupt*/
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pr_debug("MDMA:Got an interrupt on irq %d\n", irq);
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if (!mid) {
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pr_err("ERR_MDMA:null pointer mid\n");
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return -EINVAL;
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}
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pr_debug("MDMA: Status %x, Mask %x\n", tfr_status, mid->intr_mask);
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tfr_status &= mid->intr_mask;
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if (tfr_status) {
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