cxgb4: Initialize T5
Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Santosh Rastapur
David S. Miller
parent
2422d9a327
commit
0a57a5366a
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@ -233,7 +233,9 @@ static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
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};
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#define FW_FNAME "cxgb4/t4fw.bin"
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#define FW5_FNAME "cxgb4/t5fw.bin"
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#define FW_CFNAME "cxgb4/t4-config.txt"
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#define FW5_CFNAME "cxgb4/t5-config.txt"
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MODULE_DESCRIPTION(DRV_DESC);
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MODULE_AUTHOR("Chelsio Communications");
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@ -241,6 +243,7 @@ MODULE_LICENSE("Dual BSD/GPL");
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MODULE_VERSION(DRV_VERSION);
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MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
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MODULE_FIRMWARE(FW_FNAME);
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MODULE_FIRMWARE(FW5_FNAME);
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/*
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* Normally we're willing to become the firmware's Master PF but will be happy
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@ -319,10 +322,14 @@ static bool vf_acls;
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module_param(vf_acls, bool, 0644);
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MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
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static unsigned int num_vf[4];
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/* Since T5 has more num of PFs, using NUM_OF_PF_WITH_SRIOV_T5
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* macro as num_vf array size
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*/
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static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV_T5];
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module_param_array(num_vf, uint, NULL, 0644);
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MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
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MODULE_PARM_DESC(num_vf,
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"number of VFs for each of PFs 0-3 for T4 and PFs 0-7 for T5");
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#endif
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/*
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@ -1002,21 +1009,36 @@ freeout: t4_free_sge_resources(adap);
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static int upgrade_fw(struct adapter *adap)
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{
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int ret;
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u32 vers;
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u32 vers, exp_major;
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const struct fw_hdr *hdr;
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const struct firmware *fw;
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struct device *dev = adap->pdev_dev;
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char *fw_file_name;
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ret = request_firmware(&fw, FW_FNAME, dev);
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switch (CHELSIO_CHIP_VERSION(adap->chip)) {
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case CHELSIO_T4:
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fw_file_name = FW_FNAME;
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exp_major = FW_VERSION_MAJOR;
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break;
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case CHELSIO_T5:
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fw_file_name = FW5_FNAME;
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exp_major = FW_VERSION_MAJOR_T5;
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break;
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default:
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dev_err(dev, "Unsupported chip type, %x\n", adap->chip);
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return -EINVAL;
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}
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ret = request_firmware(&fw, fw_file_name, dev);
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if (ret < 0) {
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dev_err(dev, "unable to load firmware image " FW_FNAME
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", error %d\n", ret);
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dev_err(dev, "unable to load firmware image %s, error %d\n",
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fw_file_name, ret);
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return ret;
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}
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hdr = (const struct fw_hdr *)fw->data;
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vers = ntohl(hdr->fw_ver);
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if (FW_HDR_FW_VER_MAJOR_GET(vers) != FW_VERSION_MAJOR) {
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if (FW_HDR_FW_VER_MAJOR_GET(vers) != exp_major) {
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ret = -EINVAL; /* wrong major version, won't do */
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goto out;
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}
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@ -1024,18 +1046,15 @@ static int upgrade_fw(struct adapter *adap)
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/*
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* If the flash FW is unusable or we found something newer, load it.
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*/
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if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != FW_VERSION_MAJOR ||
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if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != exp_major ||
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vers > adap->params.fw_vers) {
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dev_info(dev, "upgrading firmware ...\n");
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ret = t4_fw_upgrade(adap, adap->mbox, fw->data, fw->size,
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/*force=*/false);
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if (!ret)
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dev_info(dev, "firmware successfully upgraded to "
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FW_FNAME " (%d.%d.%d.%d)\n",
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FW_HDR_FW_VER_MAJOR_GET(vers),
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FW_HDR_FW_VER_MINOR_GET(vers),
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FW_HDR_FW_VER_MICRO_GET(vers),
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FW_HDR_FW_VER_BUILD_GET(vers));
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dev_info(dev,
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"firmware upgraded to version %pI4 from %s\n",
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&hdr->fw_ver, fw_file_name);
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else
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dev_err(dev, "firmware upgrade failed! err=%d\n", -ret);
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} else {
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@ -1413,7 +1432,8 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
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*/
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static inline unsigned int mk_adap_vers(const struct adapter *ap)
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{
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return 4 | (ap->params.rev << 10) | (1 << 16);
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return CHELSIO_CHIP_VERSION(ap->chip) |
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(CHELSIO_CHIP_RELEASE(ap->chip) << 10) | (1 << 16);
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}
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static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
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@ -3745,6 +3765,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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unsigned long mtype = 0, maddr = 0;
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u32 finiver, finicsum, cfcsum;
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int ret, using_flash;
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char *fw_config_file, fw_config_file_path[256];
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/*
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* Reset device if necessary.
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@ -3761,7 +3782,21 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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* then use that. Otherwise, use the configuration file stored
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* in the adapter flash ...
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*/
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ret = request_firmware(&cf, FW_CFNAME, adapter->pdev_dev);
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switch (CHELSIO_CHIP_VERSION(adapter->chip)) {
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case CHELSIO_T4:
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fw_config_file = FW_CFNAME;
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break;
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case CHELSIO_T5:
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fw_config_file = FW5_CFNAME;
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break;
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default:
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dev_err(adapter->pdev_dev, "Device %d is not supported\n",
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adapter->pdev->device);
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ret = -EINVAL;
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goto bye;
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}
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ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
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if (ret < 0) {
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using_flash = 1;
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mtype = FW_MEMTYPE_CF_FLASH;
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@ -3877,6 +3912,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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if (ret < 0)
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goto bye;
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sprintf(fw_config_file_path, "/lib/firmware/%s", fw_config_file);
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/*
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* Return successfully and note that we're operating with parameters
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* not supplied by the driver, rather than from hard-wired
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@ -3887,7 +3923,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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"Configuration File %s, version %#x, computed checksum %#x\n",
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(using_flash
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? "in device FLASH"
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: "/lib/firmware/" FW_CFNAME),
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: fw_config_file_path),
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finiver, cfcsum);
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return 0;
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@ -4015,8 +4051,10 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
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*/
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{
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int pf, vf;
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int max_no_pf = is_t4(adapter->chip) ? NUM_OF_PF_WITH_SRIOV_T4 :
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NUM_OF_PF_WITH_SRIOV_T5;
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for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
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for (pf = 0; pf < max_no_pf; pf++) {
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if (num_vf[pf] <= 0)
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continue;
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@ -4814,7 +4852,8 @@ static void print_port_info(const struct net_device *dev)
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sprintf(bufp, "BASE-%s", base[pi->port_type]);
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netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
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adap->params.vpd.id, adap->params.rev, buf,
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adap->params.vpd.id,
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CHELSIO_CHIP_RELEASE(adap->params.rev), buf,
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is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
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(adap->flags & USING_MSIX) ? " MSI-X" :
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(adap->flags & USING_MSI) ? " MSI" : "");
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@ -4861,6 +4900,9 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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struct port_info *pi;
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bool highdma = false;
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struct adapter *adapter = NULL;
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#ifdef CONFIG_PCI_IOV
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int max_no_pf;
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#endif
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printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
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@ -5052,7 +5094,10 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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sriov:
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#ifdef CONFIG_PCI_IOV
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if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
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max_no_pf = is_t4(adapter->chip) ? NUM_OF_PF_WITH_SRIOV_T4 :
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NUM_OF_PF_WITH_SRIOV_T5;
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if (func < max_no_pf && num_vf[func] > 0)
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if (pci_enable_sriov(pdev, num_vf[func]) == 0)
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dev_info(&pdev->dev,
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"instantiated %u virtual functions\n",
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@ -506,10 +506,14 @@ static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q)
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static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
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{
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u32 val;
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if (q->pend_cred >= 8) {
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val = PIDX(q->pend_cred / 8);
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if (!is_t4(adap->chip))
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val |= DBTYPE(1);
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wmb();
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t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) |
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QID(q->cntxt_id) | PIDX(q->pend_cred / 8));
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QID(q->cntxt_id) | val);
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q->pend_cred &= 7;
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}
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}
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@ -1555,7 +1559,6 @@ static noinline int handle_trace_pkt(struct adapter *adap,
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const struct pkt_gl *gl)
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{
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struct sk_buff *skb;
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struct cpl_trace_pkt *p;
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skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
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if (unlikely(!skb)) {
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@ -1563,8 +1566,11 @@ static noinline int handle_trace_pkt(struct adapter *adap,
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return 0;
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}
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p = (struct cpl_trace_pkt *)skb->data;
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__skb_pull(skb, sizeof(*p));
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if (is_t4(adap->chip))
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__skb_pull(skb, sizeof(struct cpl_trace_pkt));
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else
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__skb_pull(skb, sizeof(struct cpl_t5_trace_pkt));
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skb_reset_mac_header(skb);
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skb->protocol = htons(0xffff);
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skb->dev = adap->port[0];
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@ -1625,8 +1631,10 @@ int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
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const struct cpl_rx_pkt *pkt;
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struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
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struct sge *s = &q->adap->sge;
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int cpl_trace_pkt = is_t4(q->adap->chip) ?
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CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
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if (unlikely(*(u8 *)rsp == CPL_TRACE_PKT))
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if (unlikely(*(u8 *)rsp == cpl_trace_pkt))
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return handle_trace_pkt(q->adap, si);
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pkt = (const struct cpl_rx_pkt *)rsp;
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@ -2587,11 +2595,20 @@ static int t4_sge_init_hard(struct adapter *adap)
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* Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
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* and generate an interrupt when this occurs so we can recover.
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*/
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t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
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V_HP_INT_THRESH(M_HP_INT_THRESH) |
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V_LP_INT_THRESH(M_LP_INT_THRESH),
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V_HP_INT_THRESH(dbfifo_int_thresh) |
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V_LP_INT_THRESH(dbfifo_int_thresh));
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if (is_t4(adap->chip)) {
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t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
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V_HP_INT_THRESH(M_HP_INT_THRESH) |
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V_LP_INT_THRESH(M_LP_INT_THRESH),
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V_HP_INT_THRESH(dbfifo_int_thresh) |
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V_LP_INT_THRESH(dbfifo_int_thresh));
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} else {
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t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
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V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5),
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V_LP_INT_THRESH_T5(dbfifo_int_thresh));
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t4_set_reg_field(adap, SGE_DBFIFO_STATUS2,
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V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5),
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V_HP_INT_THRESH_T5(dbfifo_int_thresh));
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}
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t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP,
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F_ENABLE_DROP);
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@ -497,9 +497,9 @@ int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
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}
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#define EEPROM_STAT_ADDR 0x7bfc
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#define VPD_LEN 512
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#define VPD_BASE 0x400
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#define VPD_BASE_OLD 0
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#define VPD_LEN 1024
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/**
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* t4_seeprom_wp - enable/disable EEPROM write protection
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@ -856,6 +856,7 @@ int t4_check_fw_version(struct adapter *adapter)
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{
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u32 api_vers[2];
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int ret, major, minor, micro;
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int exp_major, exp_minor, exp_micro;
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ret = get_fw_version(adapter, &adapter->params.fw_vers);
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if (!ret)
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@ -870,17 +871,35 @@ int t4_check_fw_version(struct adapter *adapter)
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major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers);
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minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers);
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micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers);
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memcpy(adapter->params.api_vers, api_vers,
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sizeof(adapter->params.api_vers));
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if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */
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dev_err(adapter->pdev_dev,
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"card FW has major version %u, driver wants %u\n",
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major, FW_VERSION_MAJOR);
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switch (CHELSIO_CHIP_VERSION(adapter->chip)) {
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case CHELSIO_T4:
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exp_major = FW_VERSION_MAJOR;
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exp_minor = FW_VERSION_MINOR;
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exp_micro = FW_VERSION_MICRO;
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break;
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case CHELSIO_T5:
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exp_major = FW_VERSION_MAJOR_T5;
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exp_minor = FW_VERSION_MINOR_T5;
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exp_micro = FW_VERSION_MICRO_T5;
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break;
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default:
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dev_err(adapter->pdev_dev, "Unsupported chip type, %x\n",
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adapter->chip);
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return -EINVAL;
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}
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if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO)
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memcpy(adapter->params.api_vers, api_vers,
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sizeof(adapter->params.api_vers));
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if (major != exp_major) { /* major mismatch - fail */
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dev_err(adapter->pdev_dev,
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"card FW has major version %u, driver wants %u\n",
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major, exp_major);
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return -EINVAL;
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}
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if (minor == exp_minor && micro == exp_micro)
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return 0; /* perfect match */
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/* Minor/micro version mismatch. Report it but often it's OK. */
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@ -1246,6 +1265,45 @@ static void pcie_intr_handler(struct adapter *adapter)
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{ 0 }
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};
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static struct intr_info t5_pcie_intr_info[] = {
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{ MSTGRPPERR, "Master Response Read Queue parity error",
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-1, 1 },
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{ MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
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{ MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
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{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
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{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
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{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
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{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
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{ PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
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-1, 1 },
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{ PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
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-1, 1 },
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{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
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{ MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
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{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
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{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
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{ DREQWRPERR, "PCI DMA channel write request parity error",
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-1, 1 },
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{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
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{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
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{ HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
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{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
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{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
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{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
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{ FIDPERR, "PCI FID parity error", -1, 1 },
|
||||
{ VFIDPERR, "PCI INTx clear parity error", -1, 1 },
|
||||
{ MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
|
||||
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
|
||||
{ IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
|
||||
-1, 1 },
|
||||
{ IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },
|
||||
{ RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
|
||||
{ IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
|
||||
{ TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
|
||||
{ READRSPERR, "Outbound read error", -1, 0 },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
int fat;
|
||||
|
||||
fat = t4_handle_intr_status(adapter,
|
||||
|
|
@ -1254,7 +1312,10 @@ static void pcie_intr_handler(struct adapter *adapter)
|
|||
t4_handle_intr_status(adapter,
|
||||
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
|
||||
pcie_port_intr_info) +
|
||||
t4_handle_intr_status(adapter, PCIE_INT_CAUSE, pcie_intr_info);
|
||||
t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
|
||||
is_t4(adapter->chip) ?
|
||||
pcie_intr_info : t5_pcie_intr_info);
|
||||
|
||||
if (fat)
|
||||
t4_fatal_err(adapter);
|
||||
}
|
||||
|
|
@ -1664,7 +1725,14 @@ static void ncsi_intr_handler(struct adapter *adap)
|
|||
*/
|
||||
static void xgmac_intr_handler(struct adapter *adap, int port)
|
||||
{
|
||||
u32 v = t4_read_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE));
|
||||
u32 v, int_cause_reg;
|
||||
|
||||
if (is_t4(adap->chip))
|
||||
int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE);
|
||||
else
|
||||
int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE);
|
||||
|
||||
v = t4_read_reg(adap, int_cause_reg);
|
||||
|
||||
v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
|
||||
if (!v)
|
||||
|
|
@ -2126,7 +2194,9 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
|
|||
u32 bgmap = get_mps_bg_map(adap, idx);
|
||||
|
||||
#define GET_STAT(name) \
|
||||
t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_##name##_L))
|
||||
t4_read_reg64(adap, \
|
||||
(is_t4(adap->chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
|
||||
T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
|
||||
#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
|
||||
|
||||
p->tx_octets = GET_STAT(TX_PORT_BYTES);
|
||||
|
|
@ -2205,14 +2275,26 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
|
|||
void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
|
||||
const u8 *addr)
|
||||
{
|
||||
u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
|
||||
|
||||
if (is_t4(adap->chip)) {
|
||||
mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
|
||||
mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
|
||||
port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
|
||||
} else {
|
||||
mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
|
||||
mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
|
||||
port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
|
||||
}
|
||||
|
||||
if (addr) {
|
||||
t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO),
|
||||
t4_write_reg(adap, mag_id_reg_l,
|
||||
(addr[2] << 24) | (addr[3] << 16) |
|
||||
(addr[4] << 8) | addr[5]);
|
||||
t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI),
|
||||
t4_write_reg(adap, mag_id_reg_h,
|
||||
(addr[0] << 8) | addr[1]);
|
||||
}
|
||||
t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), MAGICEN,
|
||||
t4_set_reg_field(adap, port_cfg_reg, MAGICEN,
|
||||
addr ? MAGICEN : 0);
|
||||
}
|
||||
|
||||
|
|
@ -2235,16 +2317,23 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
|
|||
u64 mask0, u64 mask1, unsigned int crc, bool enable)
|
||||
{
|
||||
int i;
|
||||
u32 port_cfg_reg;
|
||||
|
||||
if (is_t4(adap->chip))
|
||||
port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
|
||||
else
|
||||
port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
|
||||
|
||||
if (!enable) {
|
||||
t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2),
|
||||
PATEN, 0);
|
||||
t4_set_reg_field(adap, port_cfg_reg, PATEN, 0);
|
||||
return 0;
|
||||
}
|
||||
if (map > 0xff)
|
||||
return -EINVAL;
|
||||
|
||||
#define EPIO_REG(name) PORT_REG(port, XGMAC_PORT_EPIO_##name)
|
||||
#define EPIO_REG(name) \
|
||||
(is_t4(adap->chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \
|
||||
T5_PORT_REG(port, MAC_PORT_EPIO_##name))
|
||||
|
||||
t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
|
||||
t4_write_reg(adap, EPIO_REG(DATA2), mask1);
|
||||
|
|
@ -3162,6 +3251,9 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
|
|||
int i, ret;
|
||||
struct fw_vi_mac_cmd c;
|
||||
struct fw_vi_mac_exact *p;
|
||||
unsigned int max_naddr = is_t4(adap->chip) ?
|
||||
NUM_MPS_CLS_SRAM_L_INSTANCES :
|
||||
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
|
||||
|
||||
if (naddr > 7)
|
||||
return -EINVAL;
|
||||
|
|
@ -3187,8 +3279,8 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
|
|||
u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
|
||||
|
||||
if (idx)
|
||||
idx[i] = index >= NEXACT_MAC ? 0xffff : index;
|
||||
if (index < NEXACT_MAC)
|
||||
idx[i] = index >= max_naddr ? 0xffff : index;
|
||||
if (index < max_naddr)
|
||||
ret++;
|
||||
else if (hash)
|
||||
*hash |= (1ULL << hash_mac_addr(addr[i]));
|
||||
|
|
@ -3221,6 +3313,9 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|||
int ret, mode;
|
||||
struct fw_vi_mac_cmd c;
|
||||
struct fw_vi_mac_exact *p = c.u.exact;
|
||||
unsigned int max_mac_addr = is_t4(adap->chip) ?
|
||||
NUM_MPS_CLS_SRAM_L_INSTANCES :
|
||||
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
|
||||
|
||||
if (idx < 0) /* new allocation */
|
||||
idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
|
||||
|
|
@ -3238,7 +3333,7 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|||
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
|
||||
if (ret == 0) {
|
||||
ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
|
||||
if (ret >= NEXACT_MAC)
|
||||
if (ret >= max_mac_addr)
|
||||
ret = -ENOMEM;
|
||||
}
|
||||
return ret;
|
||||
|
|
@ -3547,7 +3642,8 @@ static int get_flash_params(struct adapter *adap)
|
|||
*/
|
||||
int t4_prep_adapter(struct adapter *adapter)
|
||||
{
|
||||
int ret;
|
||||
int ret, ver;
|
||||
uint16_t device_id;
|
||||
|
||||
ret = t4_wait_dev_ready(adapter);
|
||||
if (ret < 0)
|
||||
|
|
@ -3562,6 +3658,28 @@ int t4_prep_adapter(struct adapter *adapter)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Retrieve adapter's device ID
|
||||
*/
|
||||
pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
|
||||
ver = device_id >> 12;
|
||||
switch (ver) {
|
||||
case CHELSIO_T4:
|
||||
adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T4,
|
||||
adapter->params.rev);
|
||||
break;
|
||||
case CHELSIO_T5:
|
||||
adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T5,
|
||||
adapter->params.rev);
|
||||
break;
|
||||
default:
|
||||
dev_err(adapter->pdev_dev, "Device %d is not supported\n",
|
||||
device_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Reassign the updated revision field */
|
||||
adapter->params.rev = adapter->chip;
|
||||
|
||||
init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -47,7 +47,6 @@ enum {
|
|||
TCB_SIZE = 128, /* TCB size */
|
||||
NMTUS = 16, /* size of MTU table */
|
||||
NCCTRL_WIN = 32, /* # of congestion control windows */
|
||||
NEXACT_MAC = 336, /* # of exact MAC address filters */
|
||||
L2T_SIZE = 4096, /* # of L2T entries */
|
||||
MBOX_LEN = 64, /* mailbox size in bytes */
|
||||
TRACE_LEN = 112, /* length of trace data and mask */
|
||||
|
|
|
|||
Loading…
Reference in a new issue