drm/rockchip: vop: add rk3399 vop support
There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. most registers layout of this two vop is same, their framework are both VOP_FULL, the Major differences of this two is that: VOP_BIG max output resolution is 4096x2160. VOP_LIT max output resolution is 2560x1600 VOP_BIG support four windows. VOP_LIT only support two windows. RK3399 vop register layout is similar with rk3288, so some feature can reuse with rk3288. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>hifive-unleashed-5.1
Mark Yao
Sean Paul
parent
d49463ec78
commit
0a63bfd046
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@ -912,7 +912,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
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u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
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u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
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u16 vact_end = vact_st + vdisplay;
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uint32_t val;
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uint32_t pin_pol, val;
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WARN_ON(vop->event);
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@ -953,21 +953,26 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
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vop_dsp_hold_valid_irq_disable(vop);
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}
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val = 0x8;
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val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
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val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
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VOP_CTRL_SET(vop, pin_pol, val);
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pin_pol = 0x8;
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pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
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pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
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VOP_CTRL_SET(vop, pin_pol, pin_pol);
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switch (s->output_type) {
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case DRM_MODE_CONNECTOR_LVDS:
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VOP_CTRL_SET(vop, rgb_en, 1);
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VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
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break;
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case DRM_MODE_CONNECTOR_eDP:
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VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
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VOP_CTRL_SET(vop, edp_en, 1);
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break;
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case DRM_MODE_CONNECTOR_HDMIA:
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VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
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VOP_CTRL_SET(vop, hdmi_en, 1);
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break;
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case DRM_MODE_CONNECTOR_DSI:
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VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
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VOP_CTRL_SET(vop, mipi_en, 1);
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break;
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default:
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@ -49,6 +49,10 @@ struct vop_ctrl {
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struct vop_reg dither_down;
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struct vop_reg dither_up;
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struct vop_reg pin_pol;
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struct vop_reg rgb_pin_pol;
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struct vop_reg hdmi_pin_pol;
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struct vop_reg edp_pin_pol;
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struct vop_reg mipi_pin_pol;
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struct vop_reg htotal_pw;
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struct vop_reg hact_st_end;
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@ -279,11 +279,102 @@ static const struct vop_data rk3288_vop = {
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.win_size = ARRAY_SIZE(rk3288_vop_win_data),
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};
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static const struct vop_ctrl rk3399_ctrl_data = {
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.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
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.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
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.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
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.hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
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.edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
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.mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
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.dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
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.dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
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.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
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.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
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.rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
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.hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
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.edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
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.mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
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.htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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.hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
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.vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
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};
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static const int rk3399_vop_intrs[] = {
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FS_INTR,
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0, 0,
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LINE_FLAG_INTR,
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0,
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BUS_ERROR_INTR,
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0, 0, 0, 0, 0, 0, 0,
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DSP_HOLD_VALID_INTR,
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};
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static const struct vop_intr rk3399_vop_intr = {
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.intrs = rk3399_vop_intrs,
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.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
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.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
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.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
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.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
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};
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static const struct vop_reg_data rk3399_init_reg_table[] = {
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{RK3399_SYS_CTRL, 0x2000f800},
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{RK3399_DSP_CTRL0, 0x00000000},
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{RK3399_WIN0_CTRL0, 0x00000080},
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{RK3399_WIN1_CTRL0, 0x00000080},
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/* TODO: Win2/3 support multiple area function, but we haven't found
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* a suitable way to use it yet, so let's just use them as other windows
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* with only area 0 enabled.
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*/
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{RK3399_WIN2_CTRL0, 0x00000010},
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{RK3399_WIN3_CTRL0, 0x00000010},
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};
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static const struct vop_data rk3399_vop_big = {
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.init_table = rk3399_init_reg_table,
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.table_size = ARRAY_SIZE(rk3399_init_reg_table),
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.intr = &rk3399_vop_intr,
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.ctrl = &rk3399_ctrl_data,
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/*
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* rk3399 vop big windows register layout is same as rk3288.
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*/
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.win = rk3288_vop_win_data,
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.win_size = ARRAY_SIZE(rk3288_vop_win_data),
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};
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static const struct vop_win_data rk3399_vop_lit_win_data[] = {
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{ .base = 0x00, .phy = &rk3288_win01_data,
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.type = DRM_PLANE_TYPE_PRIMARY },
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{ .base = 0x00, .phy = &rk3288_win23_data,
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.type = DRM_PLANE_TYPE_CURSOR},
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};
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static const struct vop_data rk3399_vop_lit = {
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.init_table = rk3399_init_reg_table,
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.table_size = ARRAY_SIZE(rk3399_init_reg_table),
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.intr = &rk3399_vop_intr,
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.ctrl = &rk3399_ctrl_data,
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/*
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* rk3399 vop lit windows register layout is same as rk3288,
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* but cut off the win1 and win3 windows.
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*/
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.win = rk3399_vop_lit_win_data,
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.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
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};
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static const struct of_device_id vop_driver_dt_match[] = {
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{ .compatible = "rockchip,rk3036-vop",
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.data = &rk3036_vop },
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{ .compatible = "rockchip,rk3288-vop",
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.data = &rk3288_vop },
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{ .compatible = "rockchip,rk3399-vop-big",
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.data = &rk3399_vop_big },
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{ .compatible = "rockchip,rk3399-vop-lit",
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.data = &rk3399_vop_lit },
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{},
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};
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MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
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@ -166,4 +166,197 @@
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#define RK3036_HWC_LUT_ADDR 0x800
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/* rk3036 register definition end */
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/* rk3399 register definition */
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#define RK3399_REG_CFG_DONE 0x00000
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#define RK3399_VERSION_INFO 0x00004
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#define RK3399_SYS_CTRL 0x00008
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#define RK3399_SYS_CTRL1 0x0000c
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#define RK3399_DSP_CTRL0 0x00010
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#define RK3399_DSP_CTRL1 0x00014
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#define RK3399_DSP_BG 0x00018
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#define RK3399_MCU_CTRL 0x0001c
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#define RK3399_WB_CTRL0 0x00020
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#define RK3399_WB_CTRL1 0x00024
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#define RK3399_WB_YRGB_MST 0x00028
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#define RK3399_WB_CBR_MST 0x0002c
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#define RK3399_WIN0_CTRL0 0x00030
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#define RK3399_WIN0_CTRL1 0x00034
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#define RK3399_WIN0_COLOR_KEY 0x00038
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#define RK3399_WIN0_VIR 0x0003c
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#define RK3399_WIN0_YRGB_MST 0x00040
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#define RK3399_WIN0_CBR_MST 0x00044
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#define RK3399_WIN0_ACT_INFO 0x00048
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#define RK3399_WIN0_DSP_INFO 0x0004c
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#define RK3399_WIN0_DSP_ST 0x00050
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#define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054
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#define RK3399_WIN0_SCL_FACTOR_CBR 0x00058
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#define RK3399_WIN0_SCL_OFFSET 0x0005c
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#define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060
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#define RK3399_WIN0_DST_ALPHA_CTRL 0x00064
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#define RK3399_WIN0_FADING_CTRL 0x00068
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#define RK3399_WIN0_CTRL2 0x0006c
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#define RK3399_WIN1_CTRL0 0x00070
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#define RK3399_WIN1_CTRL1 0x00074
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#define RK3399_WIN1_COLOR_KEY 0x00078
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#define RK3399_WIN1_VIR 0x0007c
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#define RK3399_WIN1_YRGB_MST 0x00080
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#define RK3399_WIN1_CBR_MST 0x00084
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#define RK3399_WIN1_ACT_INFO 0x00088
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#define RK3399_WIN1_DSP_INFO 0x0008c
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#define RK3399_WIN1_DSP_ST 0x00090
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#define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094
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#define RK3399_WIN1_SCL_FACTOR_CBR 0x00098
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#define RK3399_WIN1_SCL_OFFSET 0x0009c
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#define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0
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#define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4
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#define RK3399_WIN1_FADING_CTRL 0x000a8
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#define RK3399_WIN1_CTRL2 0x000ac
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#define RK3399_WIN2_CTRL0 0x000b0
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#define RK3399_WIN2_CTRL1 0x000b4
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#define RK3399_WIN2_VIR0_1 0x000b8
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#define RK3399_WIN2_VIR2_3 0x000bc
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#define RK3399_WIN2_MST0 0x000c0
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#define RK3399_WIN2_DSP_INFO0 0x000c4
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#define RK3399_WIN2_DSP_ST0 0x000c8
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#define RK3399_WIN2_COLOR_KEY 0x000cc
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#define RK3399_WIN2_MST1 0x000d0
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#define RK3399_WIN2_DSP_INFO1 0x000d4
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#define RK3399_WIN2_DSP_ST1 0x000d8
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#define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc
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#define RK3399_WIN2_MST2 0x000e0
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#define RK3399_WIN2_DSP_INFO2 0x000e4
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#define RK3399_WIN2_DSP_ST2 0x000e8
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#define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec
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#define RK3399_WIN2_MST3 0x000f0
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#define RK3399_WIN2_DSP_INFO3 0x000f4
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#define RK3399_WIN2_DSP_ST3 0x000f8
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#define RK3399_WIN2_FADING_CTRL 0x000fc
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#define RK3399_WIN3_CTRL0 0x00100
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#define RK3399_WIN3_CTRL1 0x00104
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#define RK3399_WIN3_VIR0_1 0x00108
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#define RK3399_WIN3_VIR2_3 0x0010c
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#define RK3399_WIN3_MST0 0x00110
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#define RK3399_WIN3_DSP_INFO0 0x00114
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#define RK3399_WIN3_DSP_ST0 0x00118
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#define RK3399_WIN3_COLOR_KEY 0x0011c
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#define RK3399_WIN3_MST1 0x00120
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#define RK3399_WIN3_DSP_INFO1 0x00124
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#define RK3399_WIN3_DSP_ST1 0x00128
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#define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c
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#define RK3399_WIN3_MST2 0x00130
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#define RK3399_WIN3_DSP_INFO2 0x00134
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#define RK3399_WIN3_DSP_ST2 0x00138
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#define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c
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#define RK3399_WIN3_MST3 0x00140
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#define RK3399_WIN3_DSP_INFO3 0x00144
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#define RK3399_WIN3_DSP_ST3 0x00148
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#define RK3399_WIN3_FADING_CTRL 0x0014c
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#define RK3399_HWC_CTRL0 0x00150
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#define RK3399_HWC_CTRL1 0x00154
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#define RK3399_HWC_MST 0x00158
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#define RK3399_HWC_DSP_ST 0x0015c
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#define RK3399_HWC_SRC_ALPHA_CTRL 0x00160
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#define RK3399_HWC_DST_ALPHA_CTRL 0x00164
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#define RK3399_HWC_FADING_CTRL 0x00168
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#define RK3399_HWC_RESERVED1 0x0016c
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#define RK3399_POST_DSP_HACT_INFO 0x00170
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#define RK3399_POST_DSP_VACT_INFO 0x00174
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#define RK3399_POST_SCL_FACTOR_YRGB 0x00178
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#define RK3399_POST_RESERVED 0x0017c
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#define RK3399_POST_SCL_CTRL 0x00180
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#define RK3399_POST_DSP_VACT_INFO_F1 0x00184
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#define RK3399_DSP_HTOTAL_HS_END 0x00188
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#define RK3399_DSP_HACT_ST_END 0x0018c
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#define RK3399_DSP_VTOTAL_VS_END 0x00190
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#define RK3399_DSP_VACT_ST_END 0x00194
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#define RK3399_DSP_VS_ST_END_F1 0x00198
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#define RK3399_DSP_VACT_ST_END_F1 0x0019c
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#define RK3399_PWM_CTRL 0x001a0
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#define RK3399_PWM_PERIOD_HPR 0x001a4
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#define RK3399_PWM_DUTY_LPR 0x001a8
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#define RK3399_PWM_CNT 0x001ac
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#define RK3399_BCSH_COLOR_BAR 0x001b0
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#define RK3399_BCSH_BCS 0x001b4
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#define RK3399_BCSH_H 0x001b8
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#define RK3399_BCSH_CTRL 0x001bc
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#define RK3399_CABC_CTRL0 0x001c0
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#define RK3399_CABC_CTRL1 0x001c4
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#define RK3399_CABC_CTRL2 0x001c8
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#define RK3399_CABC_CTRL3 0x001cc
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#define RK3399_CABC_GAUSS_LINE0_0 0x001d0
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#define RK3399_CABC_GAUSS_LINE0_1 0x001d4
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#define RK3399_CABC_GAUSS_LINE1_0 0x001d8
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#define RK3399_CABC_GAUSS_LINE1_1 0x001dc
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#define RK3399_CABC_GAUSS_LINE2_0 0x001e0
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#define RK3399_CABC_GAUSS_LINE2_1 0x001e4
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#define RK3399_FRC_LOWER01_0 0x001e8
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#define RK3399_FRC_LOWER01_1 0x001ec
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#define RK3399_FRC_LOWER10_0 0x001f0
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#define RK3399_FRC_LOWER10_1 0x001f4
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#define RK3399_FRC_LOWER11_0 0x001f8
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#define RK3399_FRC_LOWER11_1 0x001fc
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#define RK3399_AFBCD0_CTRL 0x00200
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#define RK3399_AFBCD0_HDR_PTR 0x00204
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#define RK3399_AFBCD0_PIC_SIZE 0x00208
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#define RK3399_AFBCD0_STATUS 0x0020c
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#define RK3399_AFBCD1_CTRL 0x00220
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#define RK3399_AFBCD1_HDR_PTR 0x00224
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#define RK3399_AFBCD1_PIC_SIZE 0x00228
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#define RK3399_AFBCD1_STATUS 0x0022c
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#define RK3399_AFBCD2_CTRL 0x00240
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#define RK3399_AFBCD2_HDR_PTR 0x00244
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#define RK3399_AFBCD2_PIC_SIZE 0x00248
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#define RK3399_AFBCD2_STATUS 0x0024c
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#define RK3399_AFBCD3_CTRL 0x00260
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#define RK3399_AFBCD3_HDR_PTR 0x00264
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#define RK3399_AFBCD3_PIC_SIZE 0x00268
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#define RK3399_AFBCD3_STATUS 0x0026c
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#define RK3399_INTR_EN0 0x00280
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#define RK3399_INTR_CLEAR0 0x00284
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#define RK3399_INTR_STATUS0 0x00288
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#define RK3399_INTR_RAW_STATUS0 0x0028c
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#define RK3399_INTR_EN1 0x00290
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#define RK3399_INTR_CLEAR1 0x00294
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#define RK3399_INTR_STATUS1 0x00298
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#define RK3399_INTR_RAW_STATUS1 0x0029c
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#define RK3399_LINE_FLAG 0x002a0
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#define RK3399_VOP_STATUS 0x002a4
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#define RK3399_BLANKING_VALUE 0x002a8
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#define RK3399_MCU_BYPASS_PORT 0x002ac
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#define RK3399_WIN0_DSP_BG 0x002b0
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||||
#define RK3399_WIN1_DSP_BG 0x002b4
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#define RK3399_WIN2_DSP_BG 0x002b8
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||||
#define RK3399_WIN3_DSP_BG 0x002bc
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||||
#define RK3399_YUV2YUV_WIN 0x002c0
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#define RK3399_YUV2YUV_POST 0x002c4
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#define RK3399_AUTO_GATING_EN 0x002cc
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||||
#define RK3399_WIN0_CSC_COE 0x003a0
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#define RK3399_WIN1_CSC_COE 0x003c0
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||||
#define RK3399_WIN2_CSC_COE 0x003e0
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||||
#define RK3399_WIN3_CSC_COE 0x00400
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||||
#define RK3399_HWC_CSC_COE 0x00420
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||||
#define RK3399_BCSH_R2Y_CSC_COE 0x00440
|
||||
#define RK3399_BCSH_Y2R_CSC_COE 0x00460
|
||||
#define RK3399_POST_YUV2YUV_Y2R_COE 0x00480
|
||||
#define RK3399_POST_YUV2YUV_3X3_COE 0x004a0
|
||||
#define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0
|
||||
#define RK3399_WIN0_YUV2YUV_Y2R 0x004e0
|
||||
#define RK3399_WIN0_YUV2YUV_3X3 0x00500
|
||||
#define RK3399_WIN0_YUV2YUV_R2Y 0x00520
|
||||
#define RK3399_WIN1_YUV2YUV_Y2R 0x00540
|
||||
#define RK3399_WIN1_YUV2YUV_3X3 0x00560
|
||||
#define RK3399_WIN1_YUV2YUV_R2Y 0x00580
|
||||
#define RK3399_WIN2_YUV2YUV_Y2R 0x005a0
|
||||
#define RK3399_WIN2_YUV2YUV_3X3 0x005c0
|
||||
#define RK3399_WIN2_YUV2YUV_R2Y 0x005e0
|
||||
#define RK3399_WIN3_YUV2YUV_Y2R 0x00600
|
||||
#define RK3399_WIN3_YUV2YUV_3X3 0x00620
|
||||
#define RK3399_WIN3_YUV2YUV_R2Y 0x00640
|
||||
#define RK3399_WIN2_LUT_ADDR 0x01000
|
||||
#define RK3399_WIN3_LUT_ADDR 0x01400
|
||||
#define RK3399_HWC_LUT_ADDR 0x01800
|
||||
#define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00
|
||||
#define RK3399_GAMMA_LUT_ADDR 0x02000
|
||||
/* rk3399 register definition end */
|
||||
|
||||
#endif /* _ROCKCHIP_VOP_REG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue