drm/radeon/kms: add gpu init support for SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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1bd47d2e16
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0a96d72be9
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@ -1370,6 +1370,37 @@ struct cayman_asic {
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struct r100_gpu_lockup lockup;
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struct r100_gpu_lockup lockup;
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};
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};
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struct si_asic {
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unsigned max_shader_engines;
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unsigned max_pipes_per_simd;
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unsigned max_tile_pipes;
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unsigned max_simds_per_se;
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unsigned max_backends_per_se;
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unsigned max_texture_channel_caches;
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unsigned max_gprs;
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unsigned max_gs_threads;
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unsigned max_hw_contexts;
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unsigned sc_prim_fifo_size_frontend;
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unsigned sc_prim_fifo_size_backend;
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unsigned sc_hiz_tile_fifo_size;
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_shader_engines;
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unsigned num_tile_pipes;
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unsigned num_backends_per_se;
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unsigned backend_disable_mask_per_asic;
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unsigned backend_map;
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unsigned num_texture_channel_caches;
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unsigned mem_max_burst_length_bytes;
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unsigned mem_row_size_in_kb;
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unsigned shader_engine_tile_size;
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unsigned num_gpus;
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unsigned multi_gpu_tile_size;
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unsigned tile_config;
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struct r100_gpu_lockup lockup;
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};
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union radeon_asic_config {
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union radeon_asic_config {
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struct r300_asic r300;
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struct r300_asic r300;
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struct r100_asic r100;
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struct r100_asic r100;
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@ -1377,6 +1408,7 @@ union radeon_asic_config {
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struct rv770_asic rv770;
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struct rv770_asic rv770;
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struct evergreen_asic evergreen;
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struct evergreen_asic evergreen;
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struct cayman_asic cayman;
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struct cayman_asic cayman;
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struct si_asic si;
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};
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};
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/*
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/*
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File diff suppressed because it is too large
Load diff
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@ -32,9 +32,57 @@
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#define CTF_TEMP_MASK 0x0003fe00
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#define CTF_TEMP_MASK 0x0003fe00
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#define CTF_TEMP_SHIFT 9
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#define CTF_TEMP_SHIFT 9
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#define SI_MAX_SH_GPRS 256
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#define SI_MAX_TEMP_GPRS 16
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#define SI_MAX_SH_THREADS 256
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#define SI_MAX_SH_STACK_ENTRIES 4096
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#define SI_MAX_FRC_EOV_CNT 16384
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#define SI_MAX_BACKENDS 8
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#define SI_MAX_BACKENDS_MASK 0xFF
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#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
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#define SI_MAX_SIMDS 12
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#define SI_MAX_SIMDS_MASK 0x0FFF
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#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
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#define SI_MAX_PIPES 8
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#define SI_MAX_PIPES_MASK 0xFF
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#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
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#define SI_MAX_LDS_NUM 0xFFFF
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#define SI_MAX_TCC 16
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#define SI_MAX_TCC_MASK 0xFFFF
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#define DMIF_ADDR_CONFIG 0xBD4
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#define CC_SYS_RB_BACKEND_DISABLE 0xe80
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#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
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#define MC_SHARED_CHMAP 0x2004
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#define MC_SHARED_CHMAP 0x2004
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_MASK 0x0000f000
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#define NOOFCHAN_MASK 0x0000f000
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#define MC_SHARED_CHREMAP 0x2008
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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#define NOOFBANK_MASK 0x00000003
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#define NOOFRANK_SHIFT 2
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#define NOOFRANK_MASK 0x00000004
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#define NOOFROWS_SHIFT 3
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#define NOOFROWS_MASK 0x00000038
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#define NOOFCOLS_SHIFT 6
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#define NOOFCOLS_MASK 0x000000C0
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#define CHANSIZE_SHIFT 8
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#define CHANSIZE_MASK 0x00000100
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#define NOOFGROUPS_SHIFT 12
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#define NOOFGROUPS_MASK 0x00001000
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define HDP_ADDR_CONFIG 0x2F48
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#define HDP_MISC_CNTL 0x2F4C
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#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
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#define BIF_FB_EN 0x5490
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#define FB_READ_EN (1 << 0)
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#define FB_WRITE_EN (1 << 1)
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#define DC_LB_MEMORY_SPLIT 0x6b0c
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#define DC_LB_MEMORY_SPLIT 0x6b0c
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#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
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#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
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@ -51,4 +99,157 @@
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# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
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# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
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# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
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# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
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#define GRBM_CNTL 0x8000
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#define GRBM_READ_TIMEOUT(x) ((x) << 0)
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#define CP_QUEUE_THRESHOLDS 0x8760
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#define ROQ_IB1_START(x) ((x) << 0)
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#define ROQ_IB2_START(x) ((x) << 8)
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#define CP_MEQ_THRESHOLDS 0x8764
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#define MEQ1_START(x) ((x) << 0)
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#define MEQ2_START(x) ((x) << 8)
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#define CP_PERFMON_CNTL 0x87FC
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#define VGT_CACHE_INVALIDATION 0x88C4
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#define CACHE_INVALIDATION(x) ((x) << 0)
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#define VC_ONLY 0
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#define TC_ONLY 1
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#define VC_AND_TC 2
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#define AUTO_INVLD_EN(x) ((x) << 6)
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#define NO_AUTO 0
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#define ES_AUTO 1
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#define GS_AUTO 2
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#define ES_AND_GS_AUTO 3
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#define VGT_GS_VERTEX_REUSE 0x88D4
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#define VGT_NUM_INSTANCES 0x8974
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#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
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#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
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#define PA_CL_ENHANCE 0x8A14
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#define CLIP_VTX_REORDER_ENA (1 << 0)
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#define NUM_CLIP_SEQ(x) ((x) << 1)
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#define PA_SC_LINE_STIPPLE_STATE 0x8B10
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#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
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#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
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#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
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#define PA_SC_FIFO_SIZE 0x8BCC
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#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
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#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
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#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
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#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
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#define SQ_CONFIG 0x8C00
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#define SX_DEBUG_1 0x9060
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#define SPI_CONFIG_CNTL_1 0x913C
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#define VTX_DONE_DELAY(x) ((x) << 0)
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#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
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#define CGTS_TCC_DISABLE 0x9148
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#define CGTS_USER_TCC_DISABLE 0x914C
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#define TCC_DISABLE_MASK 0xFFFF0000
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#define TCC_DISABLE_SHIFT 16
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#define CC_RB_BACKEND_DISABLE 0x98F4
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#define BACKEND_DISABLE(x) ((x) << 16)
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#define GB_ADDR_CONFIG 0x98F8
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#define NUM_PIPES(x) ((x) << 0)
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#define NUM_PIPES_MASK 0x00000007
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#define NUM_PIPES_SHIFT 0
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#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
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#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
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#define PIPE_INTERLEAVE_SIZE_SHIFT 4
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#define NUM_SHADER_ENGINES(x) ((x) << 12)
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#define NUM_SHADER_ENGINES_MASK 0x00003000
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#define NUM_SHADER_ENGINES_SHIFT 12
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#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
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#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
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#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
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#define NUM_GPUS(x) ((x) << 20)
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#define NUM_GPUS_MASK 0x00700000
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#define NUM_GPUS_SHIFT 20
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#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
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#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
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#define MULTI_GPU_TILE_SIZE_SHIFT 24
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#define ROW_SIZE(x) ((x) << 28)
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#define ROW_SIZE_MASK 0x30000000
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#define ROW_SIZE_SHIFT 28
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#define GB_TILE_MODE0 0x9910
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# define MICRO_TILE_MODE(x) ((x) << 0)
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# define ADDR_SURF_DISPLAY_MICRO_TILING 0
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# define ADDR_SURF_THIN_MICRO_TILING 1
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# define ADDR_SURF_DEPTH_MICRO_TILING 2
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# define ARRAY_MODE(x) ((x) << 2)
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# define ARRAY_LINEAR_GENERAL 0
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# define ARRAY_LINEAR_ALIGNED 1
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# define ARRAY_1D_TILED_THIN1 2
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# define ARRAY_2D_TILED_THIN1 4
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# define PIPE_CONFIG(x) ((x) << 6)
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# define ADDR_SURF_P2 0
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# define ADDR_SURF_P4_8x16 4
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# define ADDR_SURF_P4_16x16 5
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# define ADDR_SURF_P4_16x32 6
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# define ADDR_SURF_P4_32x32 7
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# define ADDR_SURF_P8_16x16_8x16 8
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# define ADDR_SURF_P8_16x32_8x16 9
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# define ADDR_SURF_P8_32x32_8x16 10
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# define ADDR_SURF_P8_16x32_16x16 11
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# define ADDR_SURF_P8_32x32_16x16 12
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# define ADDR_SURF_P8_32x32_16x32 13
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# define ADDR_SURF_P8_32x64_32x32 14
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# define TILE_SPLIT(x) ((x) << 11)
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# define ADDR_SURF_TILE_SPLIT_64B 0
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# define ADDR_SURF_TILE_SPLIT_128B 1
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# define ADDR_SURF_TILE_SPLIT_256B 2
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# define ADDR_SURF_TILE_SPLIT_512B 3
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# define ADDR_SURF_TILE_SPLIT_1KB 4
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# define ADDR_SURF_TILE_SPLIT_2KB 5
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# define ADDR_SURF_TILE_SPLIT_4KB 6
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# define BANK_WIDTH(x) ((x) << 14)
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# define ADDR_SURF_BANK_WIDTH_1 0
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# define ADDR_SURF_BANK_WIDTH_2 1
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# define ADDR_SURF_BANK_WIDTH_4 2
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# define ADDR_SURF_BANK_WIDTH_8 3
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# define BANK_HEIGHT(x) ((x) << 16)
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# define ADDR_SURF_BANK_HEIGHT_1 0
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# define ADDR_SURF_BANK_HEIGHT_2 1
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# define ADDR_SURF_BANK_HEIGHT_4 2
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# define ADDR_SURF_BANK_HEIGHT_8 3
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# define MACRO_TILE_ASPECT(x) ((x) << 18)
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# define ADDR_SURF_MACRO_ASPECT_1 0
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# define ADDR_SURF_MACRO_ASPECT_2 1
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# define ADDR_SURF_MACRO_ASPECT_4 2
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# define ADDR_SURF_MACRO_ASPECT_8 3
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# define NUM_BANKS(x) ((x) << 20)
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# define ADDR_SURF_2_BANK 0
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# define ADDR_SURF_4_BANK 1
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# define ADDR_SURF_8_BANK 2
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# define ADDR_SURF_16_BANK 3
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#define CB_PERFCOUNTER0_SELECT0 0x9a20
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#define CB_PERFCOUNTER0_SELECT1 0x9a24
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#define CB_PERFCOUNTER1_SELECT0 0x9a28
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#define CB_PERFCOUNTER1_SELECT1 0x9a2c
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#define CB_PERFCOUNTER2_SELECT0 0x9a30
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#define CB_PERFCOUNTER2_SELECT1 0x9a34
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#define CB_PERFCOUNTER3_SELECT0 0x9a38
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#define CB_PERFCOUNTER3_SELECT1 0x9a3c
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#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
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#define BACKEND_DISABLE_MASK 0x00FF0000
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#define BACKEND_DISABLE_SHIFT 16
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#define TCP_CHAN_STEER_LO 0xac0c
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#define TCP_CHAN_STEER_HI 0xac10
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#endif
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#endif
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