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MIPS: SNI: Convert to new irq_chip functions 

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2206/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Thomas Gleixner 2011-03-23 21:09:15 +00:00 committed by Ralf Baechle
parent d6d5d5c4af
commit 0b888c7f3a
4 changed files with 33 additions and 74 deletions
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23
arch/mips/sni/a20r.c
View File

@ -168,33 +168,22 @@ static u32 a20r_ack_hwint(void)
return status; return status;
} }
static inline void unmask_a20r_irq(unsigned int irq) static inline void unmask_a20r_irq(struct irq_data *d)
{ {
set_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE)); set_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
irq_enable_hazard(); irq_enable_hazard();
} }
static inline void mask_a20r_irq(unsigned int irq) static inline void mask_a20r_irq(struct irq_data *d)
{ {
clear_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE)); clear_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
irq_disable_hazard(); irq_disable_hazard();
} }
static void end_a20r_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
a20r_ack_hwint();
unmask_a20r_irq(irq);
}
}
static struct irq_chip a20r_irq_type = { static struct irq_chip a20r_irq_type = {
.name = "A20R", .name = "A20R",
.ack = mask_a20r_irq, .irq_mask = mask_a20r_irq,
.mask = mask_a20r_irq, .irq_unmask = unmask_a20r_irq,
.mask_ack = mask_a20r_irq,
.unmask = unmask_a20r_irq,
.end = end_a20r_irq,
}; };
/* /*

21
arch/mips/sni/pcimt.c
View File

@ -194,33 +194,24 @@ static struct pci_controller sni_controller = {
.io_map_base = SNI_PORT_BASE .io_map_base = SNI_PORT_BASE
}; };
static void enable_pcimt_irq(unsigned int irq) static void enable_pcimt_irq(struct irq_data *d)
{ {
unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); unsigned int mask = 1 << (d->irq - PCIMT_IRQ_INT2);
*(volatile u8 *) PCIMT_IRQSEL |= mask; *(volatile u8 *) PCIMT_IRQSEL |= mask;
} }
void disable_pcimt_irq(unsigned int irq) void disable_pcimt_irq(struct irq_data *d)
{ {
unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); unsigned int mask = ~(1 << (d->irq - PCIMT_IRQ_INT2));
*(volatile u8 *) PCIMT_IRQSEL &= mask; *(volatile u8 *) PCIMT_IRQSEL &= mask;
} }
static void end_pcimt_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_pcimt_irq(irq);
}
static struct irq_chip pcimt_irq_type = { static struct irq_chip pcimt_irq_type = {
.name = "PCIMT", .name = "PCIMT",
.ack = disable_pcimt_irq, .irq_mask = disable_pcimt_irq,
.mask = disable_pcimt_irq, .irq_unmask = enable_pcimt_irq,
.mask_ack = disable_pcimt_irq,
.unmask = enable_pcimt_irq,
.end = end_pcimt_irq,
}; };
/* /*

21
arch/mips/sni/pcit.c
View File

@ -156,33 +156,24 @@ static struct pci_controller sni_pcit_controller = {
.io_map_base = SNI_PORT_BASE .io_map_base = SNI_PORT_BASE
}; };
static void enable_pcit_irq(unsigned int irq) static void enable_pcit_irq(struct irq_data *d)
{ {
u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24); u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
*(volatile u32 *)SNI_PCIT_INT_REG |= mask; *(volatile u32 *)SNI_PCIT_INT_REG |= mask;
} }
void disable_pcit_irq(unsigned int irq) void disable_pcit_irq(struct irq_data *d)
{ {
u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24); u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
*(volatile u32 *)SNI_PCIT_INT_REG &= ~mask; *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
} }
void end_pcit_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_pcit_irq(irq);
}
static struct irq_chip pcit_irq_type = { static struct irq_chip pcit_irq_type = {
.name = "PCIT", .name = "PCIT",
.ack = disable_pcit_irq, .irq_mask = disable_pcit_irq,
.mask = disable_pcit_irq, .irq_unmask = enable_pcit_irq,
.mask_ack = disable_pcit_irq,
.unmask = enable_pcit_irq,
.end = end_pcit_irq,
}; };
static void pcit_hwint1(void) static void pcit_hwint1(void)

42
arch/mips/sni/rm200.c
View File

@ -155,12 +155,11 @@ static __iomem u8 *rm200_pic_slave;
#define cached_master_mask (rm200_cached_irq_mask) #define cached_master_mask (rm200_cached_irq_mask)
#define cached_slave_mask (rm200_cached_irq_mask >> 8) #define cached_slave_mask (rm200_cached_irq_mask >> 8)
static void sni_rm200_disable_8259A_irq(unsigned int irq) static void sni_rm200_disable_8259A_irq(struct irq_data *d)
{ {
unsigned int mask; unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE;
unsigned long flags; unsigned long flags;
irq -= RM200_I8259A_IRQ_BASE;
mask = 1 << irq; mask = 1 << irq;
raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
rm200_cached_irq_mask |= mask; rm200_cached_irq_mask |= mask;
@ -171,12 +170,11 @@ static void sni_rm200_disable_8259A_irq(unsigned int irq)
raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
} }
static void sni_rm200_enable_8259A_irq(unsigned int irq) static void sni_rm200_enable_8259A_irq(struct irq_data *d)
{ {
unsigned int mask; unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE;
unsigned long flags; unsigned long flags;
irq -= RM200_I8259A_IRQ_BASE;
mask = ~(1 << irq); mask = ~(1 << irq);
raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
rm200_cached_irq_mask &= mask; rm200_cached_irq_mask &= mask;
@ -210,12 +208,11 @@ static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
* first, _then_ send the EOI, and the order of EOI * first, _then_ send the EOI, and the order of EOI
* to the two 8259s is important! * to the two 8259s is important!
*/ */
void sni_rm200_mask_and_ack_8259A(unsigned int irq) void sni_rm200_mask_and_ack_8259A(struct irq_data *d)
{ {
unsigned int irqmask; unsigned int irqmask, irq = d->irq - RM200_I8259A_IRQ_BASE;
unsigned long flags; unsigned long flags;
irq -= RM200_I8259A_IRQ_BASE;
irqmask = 1 << irq; irqmask = 1 << irq;
raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
/* /*
@ -285,9 +282,9 @@ spurious_8259A_irq:
static struct irq_chip sni_rm200_i8259A_chip = { static struct irq_chip sni_rm200_i8259A_chip = {
.name = "RM200-XT-PIC", .name = "RM200-XT-PIC",
.mask = sni_rm200_disable_8259A_irq, .irq_mask = sni_rm200_disable_8259A_irq,
.unmask = sni_rm200_enable_8259A_irq, .irq_unmask = sni_rm200_enable_8259A_irq,
.mask_ack = sni_rm200_mask_and_ack_8259A, .irq_mask_ack = sni_rm200_mask_and_ack_8259A,
}; };
/* /*
@ -429,33 +426,24 @@ void __init sni_rm200_i8259_irqs(void)
#define SNI_RM200_INT_START 24 #define SNI_RM200_INT_START 24
#define SNI_RM200_INT_END 28 #define SNI_RM200_INT_END 28
static void enable_rm200_irq(unsigned int irq) static void enable_rm200_irq(struct irq_data *d)
{ {
unsigned int mask = 1 << (irq - SNI_RM200_INT_START); unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START);
*(volatile u8 *)SNI_RM200_INT_ENA_REG &= ~mask; *(volatile u8 *)SNI_RM200_INT_ENA_REG &= ~mask;
} }
void disable_rm200_irq(unsigned int irq) void disable_rm200_irq(struct irq_data *d)
{ {
unsigned int mask = 1 << (irq - SNI_RM200_INT_START); unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START);
*(volatile u8 *)SNI_RM200_INT_ENA_REG |= mask; *(volatile u8 *)SNI_RM200_INT_ENA_REG |= mask;
} }
void end_rm200_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_rm200_irq(irq);
}
static struct irq_chip rm200_irq_type = { static struct irq_chip rm200_irq_type = {
.name = "RM200", .name = "RM200",
.ack = disable_rm200_irq, .irq_mask = disable_rm200_irq,
.mask = disable_rm200_irq, .irq_unmask = enable_rm200_irq,
.mask_ack = disable_rm200_irq,
.unmask = enable_rm200_irq,
.end = end_rm200_irq,
}; };
static void sni_rm200_hwint(void) static void sni_rm200_hwint(void)