drm/i915: Rename intel_engine_cs function parameters
@@
identifier func;
@@
func(..., struct intel_engine_cs *
- ring
+ engine
, ...)
{
<...
- ring
+ engine
...>
}
@@
identifier func;
type T;
@@
T func(..., struct intel_engine_cs *
- ring
+ engine
, ...);
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
hifive-unleashed-5.1
Tvrtko Ursulin
parent
e2f8039147
commit
0bc40be85f
|
|
@ -555,7 +555,7 @@ static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
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return 0;
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}
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static bool validate_cmds_sorted(struct intel_engine_cs *ring,
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static bool validate_cmds_sorted(struct intel_engine_cs *engine,
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const struct drm_i915_cmd_table *cmd_tables,
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int cmd_table_count)
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{
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@ -577,7 +577,7 @@ static bool validate_cmds_sorted(struct intel_engine_cs *ring,
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if (curr < previous) {
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DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
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ring->id, i, j, curr, previous);
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engine->id, i, j, curr, previous);
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ret = false;
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}
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@ -611,11 +611,11 @@ static bool check_sorted(int ring_id,
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return ret;
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}
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static bool validate_regs_sorted(struct intel_engine_cs *ring)
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static bool validate_regs_sorted(struct intel_engine_cs *engine)
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{
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return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
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check_sorted(ring->id, ring->master_reg_table,
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ring->master_reg_count);
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return check_sorted(engine->id, engine->reg_table, engine->reg_count) &&
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check_sorted(engine->id, engine->master_reg_table,
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engine->master_reg_count);
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}
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struct cmd_node {
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@ -639,13 +639,13 @@ struct cmd_node {
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*/
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#define CMD_HASH_MASK STD_MI_OPCODE_MASK
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static int init_hash_table(struct intel_engine_cs *ring,
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static int init_hash_table(struct intel_engine_cs *engine,
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const struct drm_i915_cmd_table *cmd_tables,
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int cmd_table_count)
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{
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int i, j;
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hash_init(ring->cmd_hash);
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hash_init(engine->cmd_hash);
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for (i = 0; i < cmd_table_count; i++) {
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const struct drm_i915_cmd_table *table = &cmd_tables[i];
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@ -660,7 +660,7 @@ static int init_hash_table(struct intel_engine_cs *ring,
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return -ENOMEM;
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desc_node->desc = desc;
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hash_add(ring->cmd_hash, &desc_node->node,
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hash_add(engine->cmd_hash, &desc_node->node,
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desc->cmd.value & CMD_HASH_MASK);
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}
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}
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@ -668,13 +668,13 @@ static int init_hash_table(struct intel_engine_cs *ring,
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return 0;
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}
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static void fini_hash_table(struct intel_engine_cs *ring)
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static void fini_hash_table(struct intel_engine_cs *engine)
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{
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struct hlist_node *tmp;
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struct cmd_node *desc_node;
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int i;
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hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) {
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hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
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hash_del(&desc_node->node);
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kfree(desc_node);
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}
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@ -690,18 +690,18 @@ static void fini_hash_table(struct intel_engine_cs *ring)
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*
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* Return: non-zero if initialization fails
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*/
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int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
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int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
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{
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const struct drm_i915_cmd_table *cmd_tables;
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int cmd_table_count;
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int ret;
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if (!IS_GEN7(ring->dev))
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if (!IS_GEN7(engine->dev))
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return 0;
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switch (ring->id) {
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switch (engine->id) {
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case RCS:
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if (IS_HASWELL(ring->dev)) {
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if (IS_HASWELL(engine->dev)) {
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cmd_tables = hsw_render_ring_cmds;
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cmd_table_count =
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ARRAY_SIZE(hsw_render_ring_cmds);
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@ -710,26 +710,26 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
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cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
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}
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ring->reg_table = gen7_render_regs;
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ring->reg_count = ARRAY_SIZE(gen7_render_regs);
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engine->reg_table = gen7_render_regs;
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engine->reg_count = ARRAY_SIZE(gen7_render_regs);
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if (IS_HASWELL(ring->dev)) {
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ring->master_reg_table = hsw_master_regs;
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ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
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if (IS_HASWELL(engine->dev)) {
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engine->master_reg_table = hsw_master_regs;
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engine->master_reg_count = ARRAY_SIZE(hsw_master_regs);
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} else {
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ring->master_reg_table = ivb_master_regs;
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ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
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engine->master_reg_table = ivb_master_regs;
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engine->master_reg_count = ARRAY_SIZE(ivb_master_regs);
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}
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ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
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engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
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break;
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case VCS:
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cmd_tables = gen7_video_cmds;
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cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
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ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
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engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
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break;
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case BCS:
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if (IS_HASWELL(ring->dev)) {
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if (IS_HASWELL(engine->dev)) {
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cmd_tables = hsw_blt_ring_cmds;
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cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
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} else {
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@ -737,44 +737,44 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
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cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
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}
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ring->reg_table = gen7_blt_regs;
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ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
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engine->reg_table = gen7_blt_regs;
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engine->reg_count = ARRAY_SIZE(gen7_blt_regs);
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if (IS_HASWELL(ring->dev)) {
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ring->master_reg_table = hsw_master_regs;
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ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
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if (IS_HASWELL(engine->dev)) {
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engine->master_reg_table = hsw_master_regs;
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engine->master_reg_count = ARRAY_SIZE(hsw_master_regs);
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} else {
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ring->master_reg_table = ivb_master_regs;
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ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
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engine->master_reg_table = ivb_master_regs;
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engine->master_reg_count = ARRAY_SIZE(ivb_master_regs);
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}
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ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
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engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
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break;
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case VECS:
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cmd_tables = hsw_vebox_cmds;
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cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
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/* VECS can use the same length_mask function as VCS */
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ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
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engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
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break;
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default:
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DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
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ring->id);
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engine->id);
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BUG();
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}
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BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
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BUG_ON(!validate_regs_sorted(ring));
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BUG_ON(!validate_cmds_sorted(engine, cmd_tables, cmd_table_count));
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BUG_ON(!validate_regs_sorted(engine));
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WARN_ON(!hash_empty(ring->cmd_hash));
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WARN_ON(!hash_empty(engine->cmd_hash));
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ret = init_hash_table(ring, cmd_tables, cmd_table_count);
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ret = init_hash_table(engine, cmd_tables, cmd_table_count);
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if (ret) {
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DRM_ERROR("CMD: cmd_parser_init failed!\n");
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fini_hash_table(ring);
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fini_hash_table(engine);
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return ret;
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}
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ring->needs_cmd_parser = true;
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engine->needs_cmd_parser = true;
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return 0;
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}
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@ -786,21 +786,21 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
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* Releases any resources related to command parsing that may have been
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* initialized for the specified ring.
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*/
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void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring)
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void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine)
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{
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if (!ring->needs_cmd_parser)
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if (!engine->needs_cmd_parser)
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return;
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fini_hash_table(ring);
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fini_hash_table(engine);
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}
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static const struct drm_i915_cmd_descriptor*
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find_cmd_in_table(struct intel_engine_cs *ring,
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find_cmd_in_table(struct intel_engine_cs *engine,
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u32 cmd_header)
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{
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struct cmd_node *desc_node;
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hash_for_each_possible(ring->cmd_hash, desc_node, node,
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hash_for_each_possible(engine->cmd_hash, desc_node, node,
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cmd_header & CMD_HASH_MASK) {
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const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
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u32 masked_cmd = desc->cmd.mask & cmd_header;
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@ -822,18 +822,18 @@ find_cmd_in_table(struct intel_engine_cs *ring,
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* ring's default length encoding and returns default_desc.
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*/
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static const struct drm_i915_cmd_descriptor*
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find_cmd(struct intel_engine_cs *ring,
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find_cmd(struct intel_engine_cs *engine,
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u32 cmd_header,
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struct drm_i915_cmd_descriptor *default_desc)
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{
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const struct drm_i915_cmd_descriptor *desc;
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u32 mask;
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desc = find_cmd_in_table(ring, cmd_header);
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desc = find_cmd_in_table(engine, cmd_header);
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if (desc)
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return desc;
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mask = ring->get_cmd_length_mask(cmd_header);
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mask = engine->get_cmd_length_mask(cmd_header);
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if (!mask)
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return NULL;
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@ -963,18 +963,18 @@ unpin_src:
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*
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* Return: true if the ring requires software command parsing
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*/
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bool i915_needs_cmd_parser(struct intel_engine_cs *ring)
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bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
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{
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if (!ring->needs_cmd_parser)
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if (!engine->needs_cmd_parser)
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return false;
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if (!USES_PPGTT(ring->dev))
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if (!USES_PPGTT(engine->dev))
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return false;
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return (i915.enable_cmd_parser == 1);
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}
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static bool check_cmd(const struct intel_engine_cs *ring,
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static bool check_cmd(const struct intel_engine_cs *engine,
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const struct drm_i915_cmd_descriptor *desc,
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const u32 *cmd, u32 length,
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const bool is_master,
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@ -1004,17 +1004,17 @@ static bool check_cmd(const struct intel_engine_cs *ring,
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offset += step) {
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const u32 reg_addr = cmd[offset] & desc->reg.mask;
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const struct drm_i915_reg_descriptor *reg =
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find_reg(ring->reg_table, ring->reg_count,
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find_reg(engine->reg_table, engine->reg_count,
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reg_addr);
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if (!reg && is_master)
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reg = find_reg(ring->master_reg_table,
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ring->master_reg_count,
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reg = find_reg(engine->master_reg_table,
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engine->master_reg_count,
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reg_addr);
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if (!reg) {
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DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
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reg_addr, *cmd, ring->id);
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reg_addr, *cmd, engine->id);
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return false;
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}
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@ -1087,7 +1087,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
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*cmd,
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desc->bits[i].mask,
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desc->bits[i].expected,
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dword, ring->id);
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dword, engine->id);
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return false;
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}
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}
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@ -1113,7 +1113,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
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* Return: non-zero if the parser finds violations or otherwise fails; -EACCES
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* if the batch appears legal but should use hardware parsing
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*/
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int i915_parse_cmds(struct intel_engine_cs *ring,
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int i915_parse_cmds(struct intel_engine_cs *engine,
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struct drm_i915_gem_object *batch_obj,
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struct drm_i915_gem_object *shadow_batch_obj,
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u32 batch_start_offset,
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@ -1147,7 +1147,7 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
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if (*cmd == MI_BATCH_BUFFER_END)
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break;
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desc = find_cmd(ring, *cmd, &default_desc);
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desc = find_cmd(engine, *cmd, &default_desc);
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if (!desc) {
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DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
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*cmd);
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@ -1179,7 +1179,7 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
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break;
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}
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if (!check_cmd(ring, desc, cmd, length, is_master,
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if (!check_cmd(engine, desc, cmd, length, is_master,
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&oacontrol_set)) {
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ret = -EINVAL;
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break;
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@ -725,11 +725,11 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
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}
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static void i915_ring_seqno_info(struct seq_file *m,
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struct intel_engine_cs *ring)
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struct intel_engine_cs *engine)
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{
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if (ring->get_seqno) {
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if (engine->get_seqno) {
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seq_printf(m, "Current sequence (%s): %x\n",
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ring->name, ring->get_seqno(ring, false));
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engine->name, engine->get_seqno(engine, false));
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}
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}
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@ -1992,22 +1992,22 @@ static int i915_context_status(struct seq_file *m, void *unused)
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static void i915_dump_lrc_obj(struct seq_file *m,
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struct intel_context *ctx,
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struct intel_engine_cs *ring)
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struct intel_engine_cs *engine)
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{
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struct page *page;
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uint32_t *reg_state;
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int j;
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struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
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struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
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unsigned long ggtt_offset = 0;
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if (ctx_obj == NULL) {
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seq_printf(m, "Context on %s with no gem object\n",
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ring->name);
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engine->name);
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return;
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}
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seq_printf(m, "CONTEXT: %s %u\n", ring->name,
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intel_execlists_ctx_id(ctx, ring));
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seq_printf(m, "CONTEXT: %s %u\n", engine->name,
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intel_execlists_ctx_id(ctx, engine));
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if (!i915_gem_obj_ggtt_bound(ctx_obj))
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seq_puts(m, "\tNot bound in GGTT\n");
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@ -2964,10 +2964,10 @@ int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
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int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
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struct drm_i915_gem_request *
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i915_gem_find_active_request(struct intel_engine_cs *ring);
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i915_gem_find_active_request(struct intel_engine_cs *engine);
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bool i915_gem_retire_requests(struct drm_device *dev);
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void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
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void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
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int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
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bool interruptible);
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@ -3297,10 +3297,10 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
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/* i915_cmd_parser.c */
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int i915_cmd_parser_get_version(void);
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int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
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void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
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bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
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int i915_parse_cmds(struct intel_engine_cs *ring,
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int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
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void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
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bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
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int i915_parse_cmds(struct intel_engine_cs *engine,
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struct drm_i915_gem_object *batch_obj,
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struct drm_i915_gem_object *shadow_batch_obj,
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u32 batch_start_offset,
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|
|
@ -3571,11 +3571,11 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
|
|||
}
|
||||
}
|
||||
|
||||
static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
|
||||
static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
|
||||
struct drm_i915_gem_request *req)
|
||||
{
|
||||
if (ring->trace_irq_req == NULL && ring->irq_get(ring))
|
||||
i915_gem_request_assign(&ring->trace_irq_req, req);
|
||||
if (engine->trace_irq_req == NULL && engine->irq_get(engine))
|
||||
i915_gem_request_assign(&engine->trace_irq_req, req);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1141,9 +1141,9 @@ static void fake_irq(unsigned long data)
|
|||
}
|
||||
|
||||
static bool missed_irq(struct drm_i915_private *dev_priv,
|
||||
struct intel_engine_cs *ring)
|
||||
struct intel_engine_cs *engine)
|
||||
{
|
||||
return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
|
||||
return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings);
|
||||
}
|
||||
|
||||
static unsigned long local_clock_us(unsigned *cpu)
|
||||
|
|
@ -2689,11 +2689,11 @@ void i915_gem_request_free(struct kref *req_ref)
|
|||
}
|
||||
|
||||
static inline int
|
||||
__i915_gem_request_alloc(struct intel_engine_cs *ring,
|
||||
__i915_gem_request_alloc(struct intel_engine_cs *engine,
|
||||
struct intel_context *ctx,
|
||||
struct drm_i915_gem_request **req_out)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(ring->dev);
|
||||
struct drm_i915_private *dev_priv = to_i915(engine->dev);
|
||||
struct drm_i915_gem_request *req;
|
||||
int ret;
|
||||
|
||||
|
|
@ -2706,13 +2706,13 @@ __i915_gem_request_alloc(struct intel_engine_cs *ring,
|
|||
if (req == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = i915_gem_get_seqno(ring->dev, &req->seqno);
|
||||
ret = i915_gem_get_seqno(engine->dev, &req->seqno);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
kref_init(&req->ref);
|
||||
req->i915 = dev_priv;
|
||||
req->ring = ring;
|
||||
req->ring = engine;
|
||||
req->ctx = ctx;
|
||||
i915_gem_context_reference(req->ctx);
|
||||
|
||||
|
|
@ -2787,11 +2787,11 @@ void i915_gem_request_cancel(struct drm_i915_gem_request *req)
|
|||
}
|
||||
|
||||
struct drm_i915_gem_request *
|
||||
i915_gem_find_active_request(struct intel_engine_cs *ring)
|
||||
i915_gem_find_active_request(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_gem_request *request;
|
||||
|
||||
list_for_each_entry(request, &ring->request_list, list) {
|
||||
list_for_each_entry(request, &engine->request_list, list) {
|
||||
if (i915_gem_request_completed(request, false))
|
||||
continue;
|
||||
|
||||
|
|
@ -2802,37 +2802,37 @@ i915_gem_find_active_request(struct intel_engine_cs *ring)
|
|||
}
|
||||
|
||||
static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
|
||||
struct intel_engine_cs *ring)
|
||||
struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_gem_request *request;
|
||||
bool ring_hung;
|
||||
|
||||
request = i915_gem_find_active_request(ring);
|
||||
request = i915_gem_find_active_request(engine);
|
||||
|
||||
if (request == NULL)
|
||||
return;
|
||||
|
||||
ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
|
||||
ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
|
||||
|
||||
i915_set_reset_status(dev_priv, request->ctx, ring_hung);
|
||||
|
||||
list_for_each_entry_continue(request, &ring->request_list, list)
|
||||
list_for_each_entry_continue(request, &engine->request_list, list)
|
||||
i915_set_reset_status(dev_priv, request->ctx, false);
|
||||
}
|
||||
|
||||
static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
|
||||
struct intel_engine_cs *ring)
|
||||
struct intel_engine_cs *engine)
|
||||
{
|
||||
struct intel_ringbuffer *buffer;
|
||||
|
||||
while (!list_empty(&ring->active_list)) {
|
||||
while (!list_empty(&engine->active_list)) {
|
||||
struct drm_i915_gem_object *obj;
|
||||
|
||||
obj = list_first_entry(&ring->active_list,
|
||||
obj = list_first_entry(&engine->active_list,
|
||||
struct drm_i915_gem_object,
|
||||
ring_list[ring->id]);
|
||||
ring_list[engine->id]);
|
||||
|
||||
i915_gem_object_retire__read(obj, ring->id);
|
||||
i915_gem_object_retire__read(obj, engine->id);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -2842,14 +2842,14 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
|
|||
*/
|
||||
|
||||
if (i915.enable_execlists) {
|
||||
spin_lock_irq(&ring->execlist_lock);
|
||||
spin_lock_irq(&engine->execlist_lock);
|
||||
|
||||
/* list_splice_tail_init checks for empty lists */
|
||||
list_splice_tail_init(&ring->execlist_queue,
|
||||
&ring->execlist_retired_req_list);
|
||||
list_splice_tail_init(&engine->execlist_queue,
|
||||
&engine->execlist_retired_req_list);
|
||||
|
||||
spin_unlock_irq(&ring->execlist_lock);
|
||||
intel_execlists_retire_requests(ring);
|
||||
spin_unlock_irq(&engine->execlist_lock);
|
||||
intel_execlists_retire_requests(engine);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -2859,10 +2859,10 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
|
|||
* implicit references on things like e.g. ppgtt address spaces through
|
||||
* the request.
|
||||
*/
|
||||
while (!list_empty(&ring->request_list)) {
|
||||
while (!list_empty(&engine->request_list)) {
|
||||
struct drm_i915_gem_request *request;
|
||||
|
||||
request = list_first_entry(&ring->request_list,
|
||||
request = list_first_entry(&engine->request_list,
|
||||
struct drm_i915_gem_request,
|
||||
list);
|
||||
|
||||
|
|
@ -2876,7 +2876,7 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
|
|||
* upon reset is less than when we start. Do one more pass over
|
||||
* all the ringbuffers to reset last_retired_head.
|
||||
*/
|
||||
list_for_each_entry(buffer, &ring->buffers, link) {
|
||||
list_for_each_entry(buffer, &engine->buffers, link) {
|
||||
buffer->last_retired_head = buffer->tail;
|
||||
intel_ring_update_space(buffer);
|
||||
}
|
||||
|
|
@ -2910,19 +2910,19 @@ void i915_gem_reset(struct drm_device *dev)
|
|||
* This function clears the request list as sequence numbers are passed.
|
||||
*/
|
||||
void
|
||||
i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
|
||||
i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
|
||||
{
|
||||
WARN_ON(i915_verify_lists(ring->dev));
|
||||
WARN_ON(i915_verify_lists(engine->dev));
|
||||
|
||||
/* Retire requests first as we use it above for the early return.
|
||||
* If we retire requests last, we may use a later seqno and so clear
|
||||
* the requests lists without clearing the active list, leading to
|
||||
* confusion.
|
||||
*/
|
||||
while (!list_empty(&ring->request_list)) {
|
||||
while (!list_empty(&engine->request_list)) {
|
||||
struct drm_i915_gem_request *request;
|
||||
|
||||
request = list_first_entry(&ring->request_list,
|
||||
request = list_first_entry(&engine->request_list,
|
||||
struct drm_i915_gem_request,
|
||||
list);
|
||||
|
||||
|
|
@ -2936,26 +2936,26 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
|
|||
* by the ringbuffer to the flushing/inactive lists as appropriate,
|
||||
* before we free the context associated with the requests.
|
||||
*/
|
||||
while (!list_empty(&ring->active_list)) {
|
||||
while (!list_empty(&engine->active_list)) {
|
||||
struct drm_i915_gem_object *obj;
|
||||
|
||||
obj = list_first_entry(&ring->active_list,
|
||||
struct drm_i915_gem_object,
|
||||
ring_list[ring->id]);
|
||||
obj = list_first_entry(&engine->active_list,
|
||||
struct drm_i915_gem_object,
|
||||
ring_list[engine->id]);
|
||||
|
||||
if (!list_empty(&obj->last_read_req[ring->id]->list))
|
||||
if (!list_empty(&obj->last_read_req[engine->id]->list))
|
||||
break;
|
||||
|
||||
i915_gem_object_retire__read(obj, ring->id);
|
||||
i915_gem_object_retire__read(obj, engine->id);
|
||||
}
|
||||
|
||||
if (unlikely(ring->trace_irq_req &&
|
||||
i915_gem_request_completed(ring->trace_irq_req, true))) {
|
||||
ring->irq_put(ring);
|
||||
i915_gem_request_assign(&ring->trace_irq_req, NULL);
|
||||
if (unlikely(engine->trace_irq_req &&
|
||||
i915_gem_request_completed(engine->trace_irq_req, true))) {
|
||||
engine->irq_put(engine);
|
||||
i915_gem_request_assign(&engine->trace_irq_req, NULL);
|
||||
}
|
||||
|
||||
WARN_ON(i915_verify_lists(ring->dev));
|
||||
WARN_ON(i915_verify_lists(engine->dev));
|
||||
}
|
||||
|
||||
bool
|
||||
|
|
@ -5022,10 +5022,10 @@ i915_gem_cleanup_ringbuffer(struct drm_device *dev)
|
|||
}
|
||||
|
||||
static void
|
||||
init_ring_lists(struct intel_engine_cs *ring)
|
||||
init_ring_lists(struct intel_engine_cs *engine)
|
||||
{
|
||||
INIT_LIST_HEAD(&ring->active_list);
|
||||
INIT_LIST_HEAD(&ring->request_list);
|
||||
INIT_LIST_HEAD(&engine->active_list);
|
||||
INIT_LIST_HEAD(&engine->request_list);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -600,7 +600,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static inline bool should_skip_switch(struct intel_engine_cs *ring,
|
||||
static inline bool should_skip_switch(struct intel_engine_cs *engine,
|
||||
struct intel_context *from,
|
||||
struct intel_context *to)
|
||||
{
|
||||
|
|
@ -608,42 +608,42 @@ static inline bool should_skip_switch(struct intel_engine_cs *ring,
|
|||
return false;
|
||||
|
||||
if (to->ppgtt && from == to &&
|
||||
!(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings))
|
||||
!(intel_ring_flag(engine) & to->ppgtt->pd_dirty_rings))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool
|
||||
needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to)
|
||||
needs_pd_load_pre(struct intel_engine_cs *engine, struct intel_context *to)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
||||
struct drm_i915_private *dev_priv = engine->dev->dev_private;
|
||||
|
||||
if (!to->ppgtt)
|
||||
return false;
|
||||
|
||||
if (INTEL_INFO(ring->dev)->gen < 8)
|
||||
if (INTEL_INFO(engine->dev)->gen < 8)
|
||||
return true;
|
||||
|
||||
if (ring != &dev_priv->ring[RCS])
|
||||
if (engine != &dev_priv->ring[RCS])
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool
|
||||
needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to,
|
||||
u32 hw_flags)
|
||||
needs_pd_load_post(struct intel_engine_cs *engine, struct intel_context *to,
|
||||
u32 hw_flags)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
||||
struct drm_i915_private *dev_priv = engine->dev->dev_private;
|
||||
|
||||
if (!to->ppgtt)
|
||||
return false;
|
||||
|
||||
if (!IS_GEN8(ring->dev))
|
||||
if (!IS_GEN8(engine->dev))
|
||||
return false;
|
||||
|
||||
if (ring != &dev_priv->ring[RCS])
|
||||
if (engine != &dev_priv->ring[RCS])
|
||||
return false;
|
||||
|
||||
if (hw_flags & MI_RESTORE_INHIBIT)
|
||||
|
|
|
|||
|
|
@ -599,7 +599,7 @@ static bool only_mappable_for_reloc(unsigned int flags)
|
|||
|
||||
static int
|
||||
i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
|
||||
struct intel_engine_cs *ring,
|
||||
struct intel_engine_cs *engine,
|
||||
bool *need_reloc)
|
||||
{
|
||||
struct drm_i915_gem_object *obj = vma->obj;
|
||||
|
|
@ -713,7 +713,7 @@ eb_vma_misplaced(struct i915_vma *vma)
|
|||
}
|
||||
|
||||
static int
|
||||
i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
|
||||
i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
|
||||
struct list_head *vmas,
|
||||
struct intel_context *ctx,
|
||||
bool *need_relocs)
|
||||
|
|
@ -723,10 +723,10 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
|
|||
struct i915_address_space *vm;
|
||||
struct list_head ordered_vmas;
|
||||
struct list_head pinned_vmas;
|
||||
bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
|
||||
bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4;
|
||||
int retry;
|
||||
|
||||
i915_gem_retire_requests_ring(ring);
|
||||
i915_gem_retire_requests_ring(engine);
|
||||
|
||||
vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
|
||||
|
||||
|
|
@ -788,7 +788,9 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
|
|||
if (eb_vma_misplaced(vma))
|
||||
ret = i915_vma_unbind(vma);
|
||||
else
|
||||
ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
|
||||
ret = i915_gem_execbuffer_reserve_vma(vma,
|
||||
engine,
|
||||
need_relocs);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
|
@ -798,7 +800,8 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
|
|||
if (drm_mm_node_allocated(&vma->node))
|
||||
continue;
|
||||
|
||||
ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
|
||||
ret = i915_gem_execbuffer_reserve_vma(vma, engine,
|
||||
need_relocs);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
|
@ -821,7 +824,7 @@ static int
|
|||
i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
|
||||
struct drm_i915_gem_execbuffer2 *args,
|
||||
struct drm_file *file,
|
||||
struct intel_engine_cs *ring,
|
||||
struct intel_engine_cs *engine,
|
||||
struct eb_vmas *eb,
|
||||
struct drm_i915_gem_exec_object2 *exec,
|
||||
struct intel_context *ctx)
|
||||
|
|
@ -910,7 +913,8 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
|
|||
goto err;
|
||||
|
||||
need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
|
||||
ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
|
||||
ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
|
||||
&need_relocs);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
|
|
@ -1062,12 +1066,12 @@ validate_exec_list(struct drm_device *dev,
|
|||
|
||||
static struct intel_context *
|
||||
i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
|
||||
struct intel_engine_cs *ring, const u32 ctx_id)
|
||||
struct intel_engine_cs *engine, const u32 ctx_id)
|
||||
{
|
||||
struct intel_context *ctx = NULL;
|
||||
struct i915_ctx_hang_stats *hs;
|
||||
|
||||
if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
|
||||
if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
ctx = i915_gem_context_get(file->driver_priv, ctx_id);
|
||||
|
|
@ -1080,8 +1084,8 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
|
|||
return ERR_PTR(-EIO);
|
||||
}
|
||||
|
||||
if (i915.enable_execlists && !ctx->engine[ring->id].state) {
|
||||
int ret = intel_lr_context_deferred_alloc(ctx, ring);
|
||||
if (i915.enable_execlists && !ctx->engine[engine->id].state) {
|
||||
int ret = intel_lr_context_deferred_alloc(ctx, engine);
|
||||
if (ret) {
|
||||
DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
|
||||
return ERR_PTR(ret);
|
||||
|
|
@ -1171,7 +1175,7 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev,
|
|||
}
|
||||
|
||||
static struct drm_i915_gem_object*
|
||||
i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
|
||||
i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
|
||||
struct drm_i915_gem_exec_object2 *shadow_exec_entry,
|
||||
struct eb_vmas *eb,
|
||||
struct drm_i915_gem_object *batch_obj,
|
||||
|
|
@ -1183,12 +1187,12 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
|
|||
struct i915_vma *vma;
|
||||
int ret;
|
||||
|
||||
shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
|
||||
shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
|
||||
PAGE_ALIGN(batch_len));
|
||||
if (IS_ERR(shadow_batch_obj))
|
||||
return shadow_batch_obj;
|
||||
|
||||
ret = i915_parse_cmds(ring,
|
||||
ret = i915_parse_cmds(engine,
|
||||
batch_obj,
|
||||
shadow_batch_obj,
|
||||
batch_start_offset,
|
||||
|
|
|
|||
|
|
@ -169,15 +169,15 @@ void i915_gem_render_state_fini(struct render_state *so)
|
|||
drm_gem_object_unreference(&so->obj->base);
|
||||
}
|
||||
|
||||
int i915_gem_render_state_prepare(struct intel_engine_cs *ring,
|
||||
int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
|
||||
struct render_state *so)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(ring->id != RCS))
|
||||
if (WARN_ON(engine->id != RCS))
|
||||
return -ENOENT;
|
||||
|
||||
ret = render_state_init(so, ring->dev);
|
||||
ret = render_state_init(so, engine->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ struct render_state {
|
|||
|
||||
int i915_gem_render_state_init(struct drm_i915_gem_request *req);
|
||||
void i915_gem_render_state_fini(struct render_state *so);
|
||||
int i915_gem_render_state_prepare(struct intel_engine_cs *ring,
|
||||
int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
|
||||
struct render_state *so);
|
||||
|
||||
#endif /* _I915_GEM_RENDER_STATE_H_ */
|
||||
|
|
|
|||
|
|
@ -842,7 +842,7 @@ static void i915_gem_record_fences(struct drm_device *dev,
|
|||
|
||||
static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
|
||||
struct drm_i915_error_state *error,
|
||||
struct intel_engine_cs *ring,
|
||||
struct intel_engine_cs *engine,
|
||||
struct drm_i915_error_ring *ering)
|
||||
{
|
||||
struct intel_engine_cs *to;
|
||||
|
|
@ -861,63 +861,64 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
|
|||
u16 signal_offset;
|
||||
u32 *tmp;
|
||||
|
||||
if (ring == to)
|
||||
if (engine == to)
|
||||
continue;
|
||||
|
||||
signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
|
||||
signal_offset = (GEN8_SIGNAL_OFFSET(engine, i) & (PAGE_SIZE - 1))
|
||||
/ 4;
|
||||
tmp = error->semaphore_obj->pages[0];
|
||||
idx = intel_ring_sync_index(ring, to);
|
||||
idx = intel_ring_sync_index(engine, to);
|
||||
|
||||
ering->semaphore_mboxes[idx] = tmp[signal_offset];
|
||||
ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
|
||||
ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
|
||||
}
|
||||
}
|
||||
|
||||
static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
|
||||
struct intel_engine_cs *ring,
|
||||
struct intel_engine_cs *engine,
|
||||
struct drm_i915_error_ring *ering)
|
||||
{
|
||||
ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
|
||||
ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
|
||||
ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
|
||||
ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
|
||||
ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
|
||||
ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
|
||||
ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
|
||||
ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
|
||||
|
||||
if (HAS_VEBOX(dev_priv->dev)) {
|
||||
ering->semaphore_mboxes[2] =
|
||||
I915_READ(RING_SYNC_2(ring->mmio_base));
|
||||
ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
|
||||
I915_READ(RING_SYNC_2(engine->mmio_base));
|
||||
ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
|
||||
}
|
||||
}
|
||||
|
||||
static void i915_record_ring_state(struct drm_device *dev,
|
||||
struct drm_i915_error_state *error,
|
||||
struct intel_engine_cs *ring,
|
||||
struct intel_engine_cs *engine,
|
||||
struct drm_i915_error_ring *ering)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (INTEL_INFO(dev)->gen >= 6) {
|
||||
ering->rc_psmi = I915_READ(RING_PSMI_CTL(ring->mmio_base));
|
||||
ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
|
||||
ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
|
||||
ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
|
||||
if (INTEL_INFO(dev)->gen >= 8)
|
||||
gen8_record_semaphore_state(dev_priv, error, ring, ering);
|
||||
gen8_record_semaphore_state(dev_priv, error, engine,
|
||||
ering);
|
||||
else
|
||||
gen6_record_semaphore_state(dev_priv, ring, ering);
|
||||
gen6_record_semaphore_state(dev_priv, engine, ering);
|
||||
}
|
||||
|
||||
if (INTEL_INFO(dev)->gen >= 4) {
|
||||
ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
|
||||
ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
|
||||
ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
|
||||
ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
|
||||
ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
|
||||
ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
|
||||
ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
|
||||
ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
|
||||
ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
|
||||
ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
|
||||
ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
|
||||
ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
|
||||
if (INTEL_INFO(dev)->gen >= 8) {
|
||||
ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
|
||||
ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
|
||||
ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
|
||||
ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
|
||||
}
|
||||
ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
|
||||
ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
|
||||
} else {
|
||||
ering->faddr = I915_READ(DMA_FADD_I8XX);
|
||||
ering->ipeir = I915_READ(IPEIR);
|
||||
|
|
@ -925,20 +926,20 @@ static void i915_record_ring_state(struct drm_device *dev,
|
|||
ering->instdone = I915_READ(GEN2_INSTDONE);
|
||||
}
|
||||
|
||||
ering->waiting = waitqueue_active(&ring->irq_queue);
|
||||
ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
|
||||
ering->seqno = ring->get_seqno(ring, false);
|
||||
ering->acthd = intel_ring_get_active_head(ring);
|
||||
ering->start = I915_READ_START(ring);
|
||||
ering->head = I915_READ_HEAD(ring);
|
||||
ering->tail = I915_READ_TAIL(ring);
|
||||
ering->ctl = I915_READ_CTL(ring);
|
||||
ering->waiting = waitqueue_active(&engine->irq_queue);
|
||||
ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
|
||||
ering->seqno = engine->get_seqno(engine, false);
|
||||
ering->acthd = intel_ring_get_active_head(engine);
|
||||
ering->start = I915_READ_START(engine);
|
||||
ering->head = I915_READ_HEAD(engine);
|
||||
ering->tail = I915_READ_TAIL(engine);
|
||||
ering->ctl = I915_READ_CTL(engine);
|
||||
|
||||
if (I915_NEED_GFX_HWS(dev)) {
|
||||
i915_reg_t mmio;
|
||||
|
||||
if (IS_GEN7(dev)) {
|
||||
switch (ring->id) {
|
||||
switch (engine->id) {
|
||||
default:
|
||||
case RCS:
|
||||
mmio = RENDER_HWS_PGA_GEN7;
|
||||
|
|
@ -953,51 +954,51 @@ static void i915_record_ring_state(struct drm_device *dev,
|
|||
mmio = VEBOX_HWS_PGA_GEN7;
|
||||
break;
|
||||
}
|
||||
} else if (IS_GEN6(ring->dev)) {
|
||||
mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
|
||||
} else if (IS_GEN6(engine->dev)) {
|
||||
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
|
||||
} else {
|
||||
/* XXX: gen8 returns to sanity */
|
||||
mmio = RING_HWS_PGA(ring->mmio_base);
|
||||
mmio = RING_HWS_PGA(engine->mmio_base);
|
||||
}
|
||||
|
||||
ering->hws = I915_READ(mmio);
|
||||
}
|
||||
|
||||
ering->hangcheck_score = ring->hangcheck.score;
|
||||
ering->hangcheck_action = ring->hangcheck.action;
|
||||
ering->hangcheck_score = engine->hangcheck.score;
|
||||
ering->hangcheck_action = engine->hangcheck.action;
|
||||
|
||||
if (USES_PPGTT(dev)) {
|
||||
int i;
|
||||
|
||||
ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
|
||||
ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
|
||||
|
||||
if (IS_GEN6(dev))
|
||||
ering->vm_info.pp_dir_base =
|
||||
I915_READ(RING_PP_DIR_BASE_READ(ring));
|
||||
I915_READ(RING_PP_DIR_BASE_READ(engine));
|
||||
else if (IS_GEN7(dev))
|
||||
ering->vm_info.pp_dir_base =
|
||||
I915_READ(RING_PP_DIR_BASE(ring));
|
||||
I915_READ(RING_PP_DIR_BASE(engine));
|
||||
else if (INTEL_INFO(dev)->gen >= 8)
|
||||
for (i = 0; i < 4; i++) {
|
||||
ering->vm_info.pdp[i] =
|
||||
I915_READ(GEN8_RING_PDP_UDW(ring, i));
|
||||
I915_READ(GEN8_RING_PDP_UDW(engine, i));
|
||||
ering->vm_info.pdp[i] <<= 32;
|
||||
ering->vm_info.pdp[i] |=
|
||||
I915_READ(GEN8_RING_PDP_LDW(ring, i));
|
||||
I915_READ(GEN8_RING_PDP_LDW(engine, i));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void i915_gem_record_active_context(struct intel_engine_cs *ring,
|
||||
static void i915_gem_record_active_context(struct intel_engine_cs *engine,
|
||||
struct drm_i915_error_state *error,
|
||||
struct drm_i915_error_ring *ering)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
||||
struct drm_i915_private *dev_priv = engine->dev->dev_private;
|
||||
struct drm_i915_gem_object *obj;
|
||||
|
||||
/* Currently render ring is the only HW context user */
|
||||
if (ring->id != RCS || !error->ccid)
|
||||
if (engine->id != RCS || !error->ccid)
|
||||
return;
|
||||
|
||||
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
||||
|
|
|
|||
|
|
@ -994,14 +994,14 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
|
|||
return;
|
||||
}
|
||||
|
||||
static void notify_ring(struct intel_engine_cs *ring)
|
||||
static void notify_ring(struct intel_engine_cs *engine)
|
||||
{
|
||||
if (!intel_ring_initialized(ring))
|
||||
if (!intel_ring_initialized(engine))
|
||||
return;
|
||||
|
||||
trace_i915_gem_request_notify(ring);
|
||||
trace_i915_gem_request_notify(engine);
|
||||
|
||||
wake_up_all(&ring->irq_queue);
|
||||
wake_up_all(&engine->irq_queue);
|
||||
}
|
||||
|
||||
static void vlv_c0_read(struct drm_i915_private *dev_priv,
|
||||
|
|
@ -1319,12 +1319,12 @@ static void snb_gt_irq_handler(struct drm_device *dev,
|
|||
}
|
||||
|
||||
static __always_inline void
|
||||
gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
|
||||
gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
|
||||
{
|
||||
if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
|
||||
notify_ring(ring);
|
||||
notify_ring(engine);
|
||||
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
|
||||
intel_lrc_irq_handler(ring);
|
||||
intel_lrc_irq_handler(engine);
|
||||
}
|
||||
|
||||
static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
|
||||
|
|
@ -2805,10 +2805,10 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
|
|||
}
|
||||
|
||||
static bool
|
||||
ring_idle(struct intel_engine_cs *ring, u32 seqno)
|
||||
ring_idle(struct intel_engine_cs *engine, u32 seqno)
|
||||
{
|
||||
return (list_empty(&ring->request_list) ||
|
||||
i915_seqno_passed(seqno, ring->last_submitted_seqno));
|
||||
return (list_empty(&engine->request_list) ||
|
||||
i915_seqno_passed(seqno, engine->last_submitted_seqno));
|
||||
}
|
||||
|
||||
static bool
|
||||
|
|
@ -2824,42 +2824,43 @@ ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
|
|||
}
|
||||
|
||||
static struct intel_engine_cs *
|
||||
semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
|
||||
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
|
||||
u64 offset)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
||||
struct drm_i915_private *dev_priv = engine->dev->dev_private;
|
||||
struct intel_engine_cs *signaller;
|
||||
int i;
|
||||
|
||||
if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
|
||||
for_each_ring(signaller, dev_priv, i) {
|
||||
if (ring == signaller)
|
||||
if (engine == signaller)
|
||||
continue;
|
||||
|
||||
if (offset == signaller->semaphore.signal_ggtt[ring->id])
|
||||
if (offset == signaller->semaphore.signal_ggtt[engine->id])
|
||||
return signaller;
|
||||
}
|
||||
} else {
|
||||
u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
|
||||
|
||||
for_each_ring(signaller, dev_priv, i) {
|
||||
if(ring == signaller)
|
||||
if(engine == signaller)
|
||||
continue;
|
||||
|
||||
if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
|
||||
if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
|
||||
return signaller;
|
||||
}
|
||||
}
|
||||
|
||||
DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
|
||||
ring->id, ipehr, offset);
|
||||
engine->id, ipehr, offset);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct intel_engine_cs *
|
||||
semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
|
||||
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
||||
struct drm_i915_private *dev_priv = engine->dev->dev_private;
|
||||
u32 cmd, ipehr, head;
|
||||
u64 offset = 0;
|
||||
int i, backwards;
|
||||
|
|
@ -2881,11 +2882,11 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
|
|||
* Therefore, this function does not support execlist mode in its
|
||||
* current form. Just return NULL and move on.
|
||||
*/
|
||||
if (ring->buffer == NULL)
|
||||
if (engine->buffer == NULL)
|
||||
return NULL;
|
||||
|
||||
ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
|
||||
if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
|
||||
ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
|
||||
if (!ipehr_is_semaphore_wait(engine->dev, ipehr))
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
|
|
@ -2896,8 +2897,8 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
|
|||
* point at at batch, and semaphores are always emitted into the
|
||||
* ringbuffer itself.
|
||||
*/
|
||||
head = I915_READ_HEAD(ring) & HEAD_ADDR;
|
||||
backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
|
||||
head = I915_READ_HEAD(engine) & HEAD_ADDR;
|
||||
backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4;
|
||||
|
||||
for (i = backwards; i; --i) {
|
||||
/*
|
||||
|
|
@ -2905,10 +2906,10 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
|
|||
* our ring is smaller than what the hardware (and hence
|
||||
* HEAD_ADDR) allows. Also handles wrap-around.
|
||||
*/
|
||||
head &= ring->buffer->size - 1;
|
||||
head &= engine->buffer->size - 1;
|
||||
|
||||
/* This here seems to blow up */
|
||||
cmd = ioread32(ring->buffer->virtual_start + head);
|
||||
cmd = ioread32(engine->buffer->virtual_start + head);
|
||||
if (cmd == ipehr)
|
||||
break;
|
||||
|
||||
|
|
@ -2918,24 +2919,24 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
|
|||
if (!i)
|
||||
return NULL;
|
||||
|
||||
*seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
|
||||
if (INTEL_INFO(ring->dev)->gen >= 8) {
|
||||
offset = ioread32(ring->buffer->virtual_start + head + 12);
|
||||
*seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
|
||||
if (INTEL_INFO(engine->dev)->gen >= 8) {
|
||||
offset = ioread32(engine->buffer->virtual_start + head + 12);
|
||||
offset <<= 32;
|
||||
offset = ioread32(ring->buffer->virtual_start + head + 8);
|
||||
offset = ioread32(engine->buffer->virtual_start + head + 8);
|
||||
}
|
||||
return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
|
||||
return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
|
||||
}
|
||||
|
||||
static int semaphore_passed(struct intel_engine_cs *ring)
|
||||
static int semaphore_passed(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
||||
struct drm_i915_private *dev_priv = engine->dev->dev_private;
|
||||
struct intel_engine_cs *signaller;
|
||||
u32 seqno;
|
||||
|
||||
ring->hangcheck.deadlock++;
|
||||
engine->hangcheck.deadlock++;
|
||||
|
||||
signaller = semaphore_waits_for(ring, &seqno);
|
||||
signaller = semaphore_waits_for(engine, &seqno);
|
||||
if (signaller == NULL)
|
||||
return -1;
|
||||
|
||||
|
|
@ -2963,16 +2964,16 @@ static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
|
|||
engine->hangcheck.deadlock = 0;
|
||||
}
|
||||
|
||||
static bool subunits_stuck(struct intel_engine_cs *ring)
|
||||
static bool subunits_stuck(struct intel_engine_cs *engine)
|
||||
{
|
||||
u32 instdone[I915_NUM_INSTDONE_REG];
|
||||
bool stuck;
|
||||
int i;
|
||||
|
||||
if (ring->id != RCS)
|
||||
if (engine->id != RCS)
|
||||
return true;
|
||||
|
||||
i915_get_extra_instdone(ring->dev, instdone);
|
||||
i915_get_extra_instdone(engine->dev, instdone);
|
||||
|
||||
/* There might be unstable subunit states even when
|
||||
* actual head is not moving. Filter out the unstable ones by
|
||||
|
|
@ -2981,44 +2982,44 @@ static bool subunits_stuck(struct intel_engine_cs *ring)
|
|||
*/
|
||||
stuck = true;
|
||||
for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
|
||||
const u32 tmp = instdone[i] | ring->hangcheck.instdone[i];
|
||||
const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
|
||||
|
||||
if (tmp != ring->hangcheck.instdone[i])
|
||||
if (tmp != engine->hangcheck.instdone[i])
|
||||
stuck = false;
|
||||
|
||||
ring->hangcheck.instdone[i] |= tmp;
|
||||
engine->hangcheck.instdone[i] |= tmp;
|
||||
}
|
||||
|
||||
return stuck;
|
||||
}
|
||||
|
||||
static enum intel_ring_hangcheck_action
|
||||
head_stuck(struct intel_engine_cs *ring, u64 acthd)
|
||||
head_stuck(struct intel_engine_cs *engine, u64 acthd)
|
||||
{
|
||||
if (acthd != ring->hangcheck.acthd) {
|
||||
if (acthd != engine->hangcheck.acthd) {
|
||||
|
||||
/* Clear subunit states on head movement */
|
||||
memset(ring->hangcheck.instdone, 0,
|
||||
sizeof(ring->hangcheck.instdone));
|
||||
memset(engine->hangcheck.instdone, 0,
|
||||
sizeof(engine->hangcheck.instdone));
|
||||
|
||||
return HANGCHECK_ACTIVE;
|
||||
}
|
||||
|
||||
if (!subunits_stuck(ring))
|
||||
if (!subunits_stuck(engine))
|
||||
return HANGCHECK_ACTIVE;
|
||||
|
||||
return HANGCHECK_HUNG;
|
||||
}
|
||||
|
||||
static enum intel_ring_hangcheck_action
|
||||
ring_stuck(struct intel_engine_cs *ring, u64 acthd)
|
||||
ring_stuck(struct intel_engine_cs *engine, u64 acthd)
|
||||
{
|
||||
struct drm_device *dev = ring->dev;
|
||||
struct drm_device *dev = engine->dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
enum intel_ring_hangcheck_action ha;
|
||||
u32 tmp;
|
||||
|
||||
ha = head_stuck(ring, acthd);
|
||||
ha = head_stuck(engine, acthd);
|
||||
if (ha != HANGCHECK_HUNG)
|
||||
return ha;
|
||||
|
||||
|
|
@ -3030,24 +3031,24 @@ ring_stuck(struct intel_engine_cs *ring, u64 acthd)
|
|||
* and break the hang. This should work on
|
||||
* all but the second generation chipsets.
|
||||
*/
|
||||
tmp = I915_READ_CTL(ring);
|
||||
tmp = I915_READ_CTL(engine);
|
||||
if (tmp & RING_WAIT) {
|
||||
i915_handle_error(dev, false,
|
||||
"Kicking stuck wait on %s",
|
||||
ring->name);
|
||||
I915_WRITE_CTL(ring, tmp);
|
||||
engine->name);
|
||||
I915_WRITE_CTL(engine, tmp);
|
||||
return HANGCHECK_KICK;
|
||||
}
|
||||
|
||||
if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
|
||||
switch (semaphore_passed(ring)) {
|
||||
switch (semaphore_passed(engine)) {
|
||||
default:
|
||||
return HANGCHECK_HUNG;
|
||||
case 1:
|
||||
i915_handle_error(dev, false,
|
||||
"Kicking stuck semaphore on %s",
|
||||
ring->name);
|
||||
I915_WRITE_CTL(ring, tmp);
|
||||
engine->name);
|
||||
I915_WRITE_CTL(engine, tmp);
|
||||
return HANGCHECK_KICK;
|
||||
case 0:
|
||||
return HANGCHECK_WAIT;
|
||||
|
|
|
|||
|
|
@ -11214,7 +11214,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool use_mmio_flip(struct intel_engine_cs *ring,
|
||||
static bool use_mmio_flip(struct intel_engine_cs *engine,
|
||||
struct drm_i915_gem_object *obj)
|
||||
{
|
||||
/*
|
||||
|
|
@ -11225,10 +11225,10 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
|
|||
* So using MMIO flips there would disrupt this mechanism.
|
||||
*/
|
||||
|
||||
if (ring == NULL)
|
||||
if (engine == NULL)
|
||||
return true;
|
||||
|
||||
if (INTEL_INFO(ring->dev)->gen < 5)
|
||||
if (INTEL_INFO(engine->dev)->gen < 5)
|
||||
return false;
|
||||
|
||||
if (i915.use_mmio_flip < 0)
|
||||
|
|
@ -11242,7 +11242,7 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
|
|||
false))
|
||||
return true;
|
||||
else
|
||||
return ring != i915_gem_request_get_ring(obj->last_write_req);
|
||||
return engine != i915_gem_request_get_ring(obj->last_write_req);
|
||||
}
|
||||
|
||||
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -57,8 +57,8 @@
|
|||
/* Logical Rings */
|
||||
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
|
||||
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
|
||||
void intel_logical_ring_stop(struct intel_engine_cs *ring);
|
||||
void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
|
||||
void intel_logical_ring_stop(struct intel_engine_cs *engine);
|
||||
void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
|
||||
int intel_logical_rings_init(struct drm_device *dev);
|
||||
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
|
||||
|
||||
|
|
@ -98,18 +98,18 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
|
|||
#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
|
||||
|
||||
void intel_lr_context_free(struct intel_context *ctx);
|
||||
uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
|
||||
uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
|
||||
int intel_lr_context_deferred_alloc(struct intel_context *ctx,
|
||||
struct intel_engine_cs *ring);
|
||||
struct intel_engine_cs *engine);
|
||||
void intel_lr_context_unpin(struct intel_context *ctx,
|
||||
struct intel_engine_cs *engine);
|
||||
void intel_lr_context_reset(struct drm_device *dev,
|
||||
struct intel_context *ctx);
|
||||
uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
|
||||
struct intel_engine_cs *ring);
|
||||
struct intel_engine_cs *engine);
|
||||
|
||||
u32 intel_execlists_ctx_id(struct intel_context *ctx,
|
||||
struct intel_engine_cs *ring);
|
||||
struct intel_engine_cs *engine);
|
||||
|
||||
/* Execlists */
|
||||
int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
|
||||
|
|
@ -118,7 +118,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
|
|||
struct drm_i915_gem_execbuffer2 *args,
|
||||
struct list_head *vmas);
|
||||
|
||||
void intel_lrc_irq_handler(struct intel_engine_cs *ring);
|
||||
void intel_execlists_retire_requests(struct intel_engine_cs *ring);
|
||||
void intel_lrc_irq_handler(struct intel_engine_cs *engine);
|
||||
void intel_execlists_retire_requests(struct intel_engine_cs *engine);
|
||||
|
||||
#endif /* _INTEL_LRC_H_ */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -355,19 +355,19 @@ struct intel_engine_cs {
|
|||
};
|
||||
|
||||
static inline bool
|
||||
intel_ring_initialized(struct intel_engine_cs *ring)
|
||||
intel_ring_initialized(struct intel_engine_cs *engine)
|
||||
{
|
||||
return ring->dev != NULL;
|
||||
return engine->dev != NULL;
|
||||
}
|
||||
|
||||
static inline unsigned
|
||||
intel_ring_flag(struct intel_engine_cs *ring)
|
||||
intel_ring_flag(struct intel_engine_cs *engine)
|
||||
{
|
||||
return 1 << ring->id;
|
||||
return 1 << engine->id;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
intel_ring_sync_index(struct intel_engine_cs *ring,
|
||||
intel_ring_sync_index(struct intel_engine_cs *engine,
|
||||
struct intel_engine_cs *other)
|
||||
{
|
||||
int idx;
|
||||
|
|
@ -380,7 +380,7 @@ intel_ring_sync_index(struct intel_engine_cs *ring,
|
|||
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
|
||||
*/
|
||||
|
||||
idx = (other - ring) - 1;
|
||||
idx = (other - engine) - 1;
|
||||
if (idx < 0)
|
||||
idx += I915_NUM_RINGS;
|
||||
|
||||
|
|
@ -388,26 +388,26 @@ intel_ring_sync_index(struct intel_engine_cs *ring,
|
|||
}
|
||||
|
||||
static inline void
|
||||
intel_flush_status_page(struct intel_engine_cs *ring, int reg)
|
||||
intel_flush_status_page(struct intel_engine_cs *engine, int reg)
|
||||
{
|
||||
drm_clflush_virt_range(&ring->status_page.page_addr[reg],
|
||||
drm_clflush_virt_range(&engine->status_page.page_addr[reg],
|
||||
sizeof(uint32_t));
|
||||
}
|
||||
|
||||
static inline u32
|
||||
intel_read_status_page(struct intel_engine_cs *ring,
|
||||
intel_read_status_page(struct intel_engine_cs *engine,
|
||||
int reg)
|
||||
{
|
||||
/* Ensure that the compiler doesn't optimize away the load. */
|
||||
barrier();
|
||||
return ring->status_page.page_addr[reg];
|
||||
return engine->status_page.page_addr[reg];
|
||||
}
|
||||
|
||||
static inline void
|
||||
intel_write_status_page(struct intel_engine_cs *ring,
|
||||
intel_write_status_page(struct intel_engine_cs *engine,
|
||||
int reg, u32 value)
|
||||
{
|
||||
ring->status_page.page_addr[reg] = value;
|
||||
engine->status_page.page_addr[reg] = value;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -438,42 +438,42 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
|
|||
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
|
||||
void intel_ringbuffer_free(struct intel_ringbuffer *ring);
|
||||
|
||||
void intel_stop_ring_buffer(struct intel_engine_cs *ring);
|
||||
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
|
||||
void intel_stop_ring_buffer(struct intel_engine_cs *engine);
|
||||
void intel_cleanup_ring_buffer(struct intel_engine_cs *engine);
|
||||
|
||||
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
|
||||
|
||||
int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
|
||||
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
|
||||
static inline void intel_ring_emit(struct intel_engine_cs *ring,
|
||||
static inline void intel_ring_emit(struct intel_engine_cs *engine,
|
||||
u32 data)
|
||||
{
|
||||
struct intel_ringbuffer *ringbuf = ring->buffer;
|
||||
struct intel_ringbuffer *ringbuf = engine->buffer;
|
||||
iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
|
||||
ringbuf->tail += 4;
|
||||
}
|
||||
static inline void intel_ring_emit_reg(struct intel_engine_cs *ring,
|
||||
static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
|
||||
i915_reg_t reg)
|
||||
{
|
||||
intel_ring_emit(ring, i915_mmio_reg_offset(reg));
|
||||
intel_ring_emit(engine, i915_mmio_reg_offset(reg));
|
||||
}
|
||||
static inline void intel_ring_advance(struct intel_engine_cs *ring)
|
||||
static inline void intel_ring_advance(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct intel_ringbuffer *ringbuf = ring->buffer;
|
||||
struct intel_ringbuffer *ringbuf = engine->buffer;
|
||||
ringbuf->tail &= ringbuf->size - 1;
|
||||
}
|
||||
int __intel_ring_space(int head, int tail, int size);
|
||||
void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
|
||||
int intel_ring_space(struct intel_ringbuffer *ringbuf);
|
||||
bool intel_ring_stopped(struct intel_engine_cs *ring);
|
||||
bool intel_ring_stopped(struct intel_engine_cs *engine);
|
||||
|
||||
int __must_check intel_ring_idle(struct intel_engine_cs *ring);
|
||||
void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
|
||||
int __must_check intel_ring_idle(struct intel_engine_cs *engine);
|
||||
void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
|
||||
int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
|
||||
int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
|
||||
|
||||
void intel_fini_pipe_control(struct intel_engine_cs *ring);
|
||||
int intel_init_pipe_control(struct intel_engine_cs *ring);
|
||||
void intel_fini_pipe_control(struct intel_engine_cs *engine);
|
||||
int intel_init_pipe_control(struct intel_engine_cs *engine);
|
||||
|
||||
int intel_init_render_ring_buffer(struct drm_device *dev);
|
||||
int intel_init_bsd_ring_buffer(struct drm_device *dev);
|
||||
|
|
@ -481,9 +481,9 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev);
|
|||
int intel_init_blt_ring_buffer(struct drm_device *dev);
|
||||
int intel_init_vebox_ring_buffer(struct drm_device *dev);
|
||||
|
||||
u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
|
||||
u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
|
||||
|
||||
int init_workarounds_ring(struct intel_engine_cs *ring);
|
||||
int init_workarounds_ring(struct intel_engine_cs *engine);
|
||||
|
||||
static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue