drm/radeon: handle lockup in delayed work, v5
v5 (chk): complete rework, start when the first fence is emitted, stop when the last fence is signalled, make it work correctly with GPU resets, cleanup radeon_fence_wait_seq Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -350,6 +350,7 @@ extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
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* Fences.
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*/
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struct radeon_fence_driver {
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struct radeon_device *rdev;
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uint32_t scratch_reg;
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uint64_t gpu_addr;
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volatile uint32_t *cpu_addr;
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@ -357,6 +358,7 @@ struct radeon_fence_driver {
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uint64_t sync_seq[RADEON_NUM_RINGS];
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atomic64_t last_seq;
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bool initialized;
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struct delayed_work lockup_work;
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};
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struct radeon_fence {
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@ -97,6 +97,25 @@ static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
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return seq;
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}
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/**
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* radeon_fence_schedule_check - schedule lockup check
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*
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* @rdev: radeon_device pointer
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* @ring: ring index we should work with
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*
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* Queues a delayed work item to check for lockups.
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*/
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static void radeon_fence_schedule_check(struct radeon_device *rdev, int ring)
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{
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/*
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* Do not reset the timer here with mod_delayed_work,
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* this can livelock in an interaction with TTM delayed destroy.
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*/
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queue_delayed_work(system_power_efficient_wq,
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&rdev->fence_drv[ring].lockup_work,
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RADEON_FENCE_JIFFIES_TIMEOUT);
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}
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/**
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* radeon_fence_emit - emit a fence on the requested ring
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*
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@ -122,19 +141,21 @@ int radeon_fence_emit(struct radeon_device *rdev,
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(*fence)->ring = ring;
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radeon_fence_ring_emit(rdev, ring, *fence);
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trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
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radeon_fence_schedule_check(rdev, ring);
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return 0;
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}
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/**
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* radeon_fence_process - process a fence
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* radeon_fence_activity - check for fence activity
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the fence is associated with
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*
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* Checks the current fence value and wakes the fence queue
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* if the sequence number has increased (all asics).
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* Checks the current fence value and calculates the last
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* signalled fence value. Returns true if activity occured
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* on the ring, and the fence_queue should be waken up.
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*/
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void radeon_fence_process(struct radeon_device *rdev, int ring)
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static bool radeon_fence_activity(struct radeon_device *rdev, int ring)
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{
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uint64_t seq, last_seq, last_emitted;
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unsigned count_loop = 0;
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@ -190,7 +211,67 @@ void radeon_fence_process(struct radeon_device *rdev, int ring)
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}
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} while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
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if (wake)
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if (seq < last_emitted)
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radeon_fence_schedule_check(rdev, ring);
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return wake;
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}
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/**
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* radeon_fence_check_lockup - check for hardware lockup
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*
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* @work: delayed work item
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*
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* Checks for fence activity and if there is none probe
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* the hardware if a lockup occured.
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*/
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static void radeon_fence_check_lockup(struct work_struct *work)
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{
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struct radeon_fence_driver *fence_drv;
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struct radeon_device *rdev;
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int ring;
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fence_drv = container_of(work, struct radeon_fence_driver,
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lockup_work.work);
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rdev = fence_drv->rdev;
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ring = fence_drv - &rdev->fence_drv[0];
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if (!down_read_trylock(&rdev->exclusive_lock)) {
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/* just reschedule the check if a reset is going on */
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radeon_fence_schedule_check(rdev, ring);
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return;
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}
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if (radeon_fence_activity(rdev, ring))
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wake_up_all(&rdev->fence_queue);
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else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
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/* good news we believe it's a lockup */
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dev_warn(rdev->dev, "GPU lockup (current fence id "
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"0x%016llx last fence id 0x%016llx on ring %d)\n",
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(uint64_t)atomic64_read(&fence_drv->last_seq),
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fence_drv->sync_seq[ring], ring);
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/* remember that we need an reset */
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rdev->needs_reset = true;
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wake_up_all(&rdev->fence_queue);
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}
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up_read(&rdev->exclusive_lock);
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}
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/**
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* radeon_fence_process - process a fence
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the fence is associated with
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*
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* Checks the current fence value and wakes the fence queue
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* if the sequence number has increased (all asics).
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*/
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void radeon_fence_process(struct radeon_device *rdev, int ring)
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{
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if (radeon_fence_activity(rdev, ring))
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wake_up_all(&rdev->fence_queue);
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}
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@ -300,86 +381,43 @@ static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
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static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
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bool intr)
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{
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uint64_t last_seq[RADEON_NUM_RINGS];
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bool signaled;
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int i, r;
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long r;
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int i;
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while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
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if (radeon_fence_any_seq_signaled(rdev, target_seq))
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return 0;
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/* Save current sequence values, used to check for GPU lockups */
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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if (!target_seq[i])
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continue;
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/* enable IRQs and tracing */
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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if (!target_seq[i])
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continue;
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last_seq[i] = atomic64_read(&rdev->fence_drv[i].last_seq);
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trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
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radeon_irq_kms_sw_irq_get(rdev, i);
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}
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if (intr) {
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r = wait_event_interruptible_timeout(rdev->fence_queue, (
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(signaled = radeon_fence_any_seq_signaled(rdev, target_seq))
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|| rdev->needs_reset), RADEON_FENCE_JIFFIES_TIMEOUT);
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} else {
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r = wait_event_timeout(rdev->fence_queue, (
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(signaled = radeon_fence_any_seq_signaled(rdev, target_seq))
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|| rdev->needs_reset), RADEON_FENCE_JIFFIES_TIMEOUT);
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}
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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if (!target_seq[i])
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continue;
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radeon_irq_kms_sw_irq_put(rdev, i);
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trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
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}
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if (unlikely(r < 0))
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return r;
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if (unlikely(!signaled)) {
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if (rdev->needs_reset)
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return -EDEADLK;
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/* we were interrupted for some reason and fence
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* isn't signaled yet, resume waiting */
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if (r)
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continue;
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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if (!target_seq[i])
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continue;
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if (last_seq[i] != atomic64_read(&rdev->fence_drv[i].last_seq))
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break;
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}
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if (i != RADEON_NUM_RINGS)
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continue;
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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if (!target_seq[i])
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continue;
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if (radeon_ring_is_lockup(rdev, i, &rdev->ring[i]))
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break;
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}
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if (i < RADEON_NUM_RINGS) {
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/* good news we believe it's a lockup */
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dev_warn(rdev->dev, "GPU lockup (waiting for "
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"0x%016llx last fence id 0x%016llx on"
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" ring %d)\n",
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target_seq[i], last_seq[i], i);
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/* remember that we need an reset */
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rdev->needs_reset = true;
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wake_up_all(&rdev->fence_queue);
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return -EDEADLK;
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}
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}
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trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
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radeon_irq_kms_sw_irq_get(rdev, i);
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}
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return 0;
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if (intr) {
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r = wait_event_interruptible_timeout(rdev->fence_queue, (
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radeon_fence_any_seq_signaled(rdev, target_seq)
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|| rdev->needs_reset), MAX_SCHEDULE_TIMEOUT);
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} else {
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r = wait_event_timeout(rdev->fence_queue, (
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radeon_fence_any_seq_signaled(rdev, target_seq)
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|| rdev->needs_reset), MAX_SCHEDULE_TIMEOUT);
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}
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if (rdev->needs_reset)
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r = -EDEADLK;
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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if (!target_seq[i])
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continue;
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radeon_irq_kms_sw_irq_put(rdev, i);
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trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
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}
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return r < 0 ? r : 0;
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}
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/**
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@ -711,6 +749,9 @@ static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
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rdev->fence_drv[ring].sync_seq[i] = 0;
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atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
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rdev->fence_drv[ring].initialized = false;
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INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,
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radeon_fence_check_lockup);
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rdev->fence_drv[ring].rdev = rdev;
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}
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/**
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@ -760,6 +801,7 @@ void radeon_fence_driver_fini(struct radeon_device *rdev)
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/* no need to trigger GPU reset as we are unloading */
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radeon_fence_driver_force_completion(rdev, ring);
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}
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cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
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wake_up_all(&rdev->fence_queue);
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radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
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rdev->fence_drv[ring].initialized = false;
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*/
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void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring)
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{
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if (rdev->fence_drv[ring].initialized)
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if (rdev->fence_drv[ring].initialized) {
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radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
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cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
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}
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}
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