mtd: rawnand: brcmnand: Add support for v7.3 controller
This change adds support for brcm NAND v7.3 controller. This controller uses a newer version of flash_dma engine and change mostly implements these differences. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>alistair/sunxi64-5.4-dsi
Kamal Dasu
Miquel Raynal
parent
3c7c1e4594
commit
0c06da5788
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@ -84,6 +84,12 @@ struct brcm_nand_dma_desc {
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#define FLASH_DMA_ECC_ERROR (1 << 8)
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#define FLASH_DMA_CORR_ERROR (1 << 9)
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/* Bitfields for DMA_MODE */
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#define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
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#define FLASH_DMA_MODE_MODE BIT(0) /* link list */
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#define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \
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FLASH_DMA_MODE_MODE)
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/* 512B flash cache in the NAND controller HW */
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#define FC_SHIFT 9U
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#define FC_BYTES 512U
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@ -96,6 +102,51 @@ struct brcm_nand_dma_desc {
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#define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
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#define NAND_POLL_STATUS_TIMEOUT_MS 100
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/* flash_dma registers */
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enum flash_dma_reg {
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FLASH_DMA_REVISION = 0,
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FLASH_DMA_FIRST_DESC,
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FLASH_DMA_FIRST_DESC_EXT,
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FLASH_DMA_CTRL,
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FLASH_DMA_MODE,
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FLASH_DMA_STATUS,
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FLASH_DMA_INTERRUPT_DESC,
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FLASH_DMA_INTERRUPT_DESC_EXT,
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FLASH_DMA_ERROR_STATUS,
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FLASH_DMA_CURRENT_DESC,
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FLASH_DMA_CURRENT_DESC_EXT,
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};
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/* flash_dma registers v1*/
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static const u16 flash_dma_regs_v1[] = {
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[FLASH_DMA_REVISION] = 0x00,
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[FLASH_DMA_FIRST_DESC] = 0x04,
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[FLASH_DMA_FIRST_DESC_EXT] = 0x08,
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[FLASH_DMA_CTRL] = 0x0c,
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[FLASH_DMA_MODE] = 0x10,
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[FLASH_DMA_STATUS] = 0x14,
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[FLASH_DMA_INTERRUPT_DESC] = 0x18,
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[FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c,
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[FLASH_DMA_ERROR_STATUS] = 0x20,
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[FLASH_DMA_CURRENT_DESC] = 0x24,
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[FLASH_DMA_CURRENT_DESC_EXT] = 0x28,
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};
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/* flash_dma registers v4 */
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static const u16 flash_dma_regs_v4[] = {
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[FLASH_DMA_REVISION] = 0x00,
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[FLASH_DMA_FIRST_DESC] = 0x08,
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[FLASH_DMA_FIRST_DESC_EXT] = 0x0c,
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[FLASH_DMA_CTRL] = 0x10,
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[FLASH_DMA_MODE] = 0x14,
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[FLASH_DMA_STATUS] = 0x18,
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[FLASH_DMA_INTERRUPT_DESC] = 0x20,
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[FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24,
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[FLASH_DMA_ERROR_STATUS] = 0x28,
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[FLASH_DMA_CURRENT_DESC] = 0x30,
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[FLASH_DMA_CURRENT_DESC_EXT] = 0x34,
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};
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/* Controller feature flags */
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enum {
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BRCMNAND_HAS_1K_SECTORS = BIT(0),
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@ -128,6 +179,8 @@ struct brcmnand_controller {
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/* List of NAND hosts (one for each chip-select) */
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struct list_head host_list;
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/* flash_dma reg */
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const u16 *flash_dma_offsets;
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struct brcm_nand_dma_desc *dma_desc;
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dma_addr_t dma_pa;
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@ -463,7 +516,7 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
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/* Register offsets */
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if (ctrl->nand_version >= 0x0702)
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ctrl->reg_offsets = brcmnand_regs_v72;
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else if (ctrl->nand_version >= 0x0701)
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else if (ctrl->nand_version == 0x0701)
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ctrl->reg_offsets = brcmnand_regs_v71;
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else if (ctrl->nand_version >= 0x0600)
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ctrl->reg_offsets = brcmnand_regs_v60;
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@ -508,7 +561,7 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
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}
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/* Maximum spare area sector size (per 512B) */
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if (ctrl->nand_version >= 0x0702)
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if (ctrl->nand_version == 0x0702)
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ctrl->max_oob = 128;
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else if (ctrl->nand_version >= 0x0600)
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ctrl->max_oob = 64;
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@ -539,6 +592,15 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
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return 0;
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}
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static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)
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{
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/* flash_dma register offsets */
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if (ctrl->nand_version >= 0x0703)
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ctrl->flash_dma_offsets = flash_dma_regs_v4;
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else
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ctrl->flash_dma_offsets = flash_dma_regs_v1;
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}
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static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
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enum brcmnand_reg reg)
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{
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@ -661,7 +723,7 @@ static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
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enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
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int cs = host->cs;
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if (ctrl->nand_version >= 0x0702)
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if (ctrl->nand_version == 0x0702)
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bits = 7;
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else if (ctrl->nand_version >= 0x0600)
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bits = 6;
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@ -715,7 +777,7 @@ enum {
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static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
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{
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if (ctrl->nand_version >= 0x0702)
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if (ctrl->nand_version == 0x0702)
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return GENMASK(7, 0);
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else if (ctrl->nand_version >= 0x0600)
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return GENMASK(6, 0);
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@ -845,20 +907,6 @@ static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
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* Flash DMA
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***********************************************************************/
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enum flash_dma_reg {
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FLASH_DMA_REVISION = 0x00,
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FLASH_DMA_FIRST_DESC = 0x04,
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FLASH_DMA_FIRST_DESC_EXT = 0x08,
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FLASH_DMA_CTRL = 0x0c,
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FLASH_DMA_MODE = 0x10,
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FLASH_DMA_STATUS = 0x14,
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FLASH_DMA_INTERRUPT_DESC = 0x18,
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FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
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FLASH_DMA_ERROR_STATUS = 0x20,
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FLASH_DMA_CURRENT_DESC = 0x24,
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FLASH_DMA_CURRENT_DESC_EXT = 0x28,
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};
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static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
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{
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return ctrl->flash_dma_base;
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@ -884,14 +932,19 @@ static inline bool flash_dma_buf_ok(const void *buf)
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likely(IS_ALIGNED((uintptr_t)buf, 4));
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}
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static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
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u32 val)
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static inline void flash_dma_writel(struct brcmnand_controller *ctrl,
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enum flash_dma_reg dma_reg, u32 val)
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{
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u16 offs = ctrl->flash_dma_offsets[dma_reg];
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brcmnand_writel(val, ctrl->flash_dma_base + offs);
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}
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static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
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static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl,
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enum flash_dma_reg dma_reg)
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{
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u16 offs = ctrl->flash_dma_offsets[dma_reg];
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return brcmnand_readl(ctrl->flash_dma_base + offs);
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}
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@ -2472,6 +2525,7 @@ static const struct of_device_id brcmnand_of_match[] = {
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{ .compatible = "brcm,brcmnand-v7.0" },
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{ .compatible = "brcm,brcmnand-v7.1" },
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{ .compatible = "brcm,brcmnand-v7.2" },
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{ .compatible = "brcm,brcmnand-v7.3" },
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{},
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};
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MODULE_DEVICE_TABLE(of, brcmnand_of_match);
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@ -2558,7 +2612,11 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
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goto err;
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}
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flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
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/* initialize the dma version */
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brcmnand_flash_dma_revision_init(ctrl);
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/* linked-list and stop on error */
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flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK);
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flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
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/* Allocate descriptor(s) */
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