clk: renesas: cpg-mssr: Add support for fixed rate clocks
Add support for defining fixed rate clocks, to be used for on-chip oscillators. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>hifive-unleashed-5.1
parent
3a251270e6
commit
0d2602d750
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@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
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}
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}
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break;
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break;
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case CLK_TYPE_FR:
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clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
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core->mult);
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break;
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default:
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default:
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if (info->cpg_clk_register)
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if (info->cpg_clk_register)
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clk = info->cpg_clk_register(dev, core, info,
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clk = info->cpg_clk_register(dev, core, info,
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@ -38,6 +38,7 @@ enum clk_types {
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
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CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
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CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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CLK_TYPE_FR, /* Fixed Rate Clock */
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/* Custom definitions start here */
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/* Custom definitions start here */
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CLK_TYPE_CUSTOM,
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CLK_TYPE_CUSTOM,
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@ -56,6 +57,8 @@ enum clk_types {
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DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
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#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
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DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
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#define DEF_RATE(_name, _id, _rate) \
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DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
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/*
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/*
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* Definitions of Module Clocks
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* Definitions of Module Clocks
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