clk: bcm2835: Don't cache the PLLB rate
The PLLB rate will be changed through the firmware clocks drivers and will change behind this drivers' back, so we don't want to cache the rate. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/9864daba2f584ed49aee5ed1d2f4d48507c58197.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -1700,7 +1700,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.min_rate = 600000000u,
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.max_rate = 3000000000u,
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.max_fb_rate = BCM2835_MAX_FB_RATE),
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.max_fb_rate = BCM2835_MAX_FB_RATE,
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.flags = CLK_GET_RATE_NOCACHE),
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[BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
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SOC_ALL,
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.name = "pllb_arm",
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@ -1710,7 +1711,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.load_mask = CM_PLLB_LOADARM,
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.hold_mask = CM_PLLB_HOLDARM,
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.fixed_divider = 1,
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.flags = CLK_SET_RATE_PARENT),
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
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/*
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* PLLC is the core PLL, used to drive the core VPU clock.
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