platform/x86: mlx-platform: Add support for next generation systems
Add support for new Mellanox system types of basic class VMOD0010, containing new Mellanox systems equipped with new switch device Spectrum 3 (32x400GbE/64x200G/128x100G Ethernet switch). These are the Top of the Rack 1U/2U/4U systems, equipped with Mellanox Comex card and with the switch board with Mellanox Spectrum-3 device. This class of devices can be equipped with two PS units for 1U/2U or with four PS units for 4U systems. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>alistair/sensors
Vadim Pasternak
Andy Shevchenko
parent
0e41bf06ee
commit
0d559d05a2
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@ -163,6 +163,7 @@
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#define MLXPLAT_CPLD_NR_NONE -1
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#define MLXPLAT_CPLD_PSU_DEFAULT_NR 10
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#define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4
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#define MLXPLAT_CPLD_PSU_MSNXXXX_NR2 3
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#define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11
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#define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12
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#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
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@ -212,8 +213,24 @@ static const struct resource mlxplat_lpc_resources[] = {
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IORESOURCE_IO),
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};
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/* Platform i2c next generation systems data */
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static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = {
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{
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
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.mask = MLXPLAT_CPLD_I2C_CAP_MASK,
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.bit = MLXPLAT_CPLD_I2C_CAP_BIT,
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},
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};
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static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = {
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{
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.data = mlxplat_mlxcpld_i2c_ng_items_data,
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},
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};
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/* Platform next generation systems i2c data */
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static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = {
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.items = mlxplat_mlxcpld_i2c_ng_items,
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.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
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.mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
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.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET,
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@ -847,6 +864,116 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = {
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.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
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};
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/* Platform hotplug extended system family data */
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static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = {
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{
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.label = "psu1",
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = BIT(0),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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{
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.label = "psu2",
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = BIT(1),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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{
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.label = "psu3",
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = BIT(2),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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{
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.label = "psu4",
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = BIT(3),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = {
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{
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.label = "pwr1",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(0),
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.hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
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.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
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},
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{
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.label = "pwr2",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(1),
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.hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
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.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
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},
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{
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.label = "pwr3",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(2),
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.hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
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.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR2,
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},
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{
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.label = "pwr4",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(3),
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.hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
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.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR2,
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},
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};
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static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
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{
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.data = mlxplat_mlxcpld_ext_psu_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = MLXPLAT_CPLD_PSU_EXT_MASK,
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.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
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.inversed = 1,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_ext_pwr_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = MLXPLAT_CPLD_PWR_EXT_MASK,
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.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
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.inversed = 0,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_ng_fan_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
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.mask = MLXPLAT_CPLD_FAN_NG_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
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.inversed = 1,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_asic_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
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.mask = MLXPLAT_CPLD_ASIC_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
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.inversed = 0,
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.health = true,
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},
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};
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static
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struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
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.items = mlxplat_mlxcpld_ext_items,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items),
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.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
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.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
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.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
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.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
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};
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/* Platform led default data */
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static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
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{
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@ -2040,6 +2167,13 @@ static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = {
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{ MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
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};
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static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = {
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{ MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
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{ MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
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{ MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
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{ MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
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};
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struct mlxplat_mlxcpld_regmap_context {
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void __iomem *base;
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};
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@ -2106,6 +2240,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = {
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.reg_write = mlxplat_mlxcpld_reg_write,
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};
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static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = 255,
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.cache_type = REGCACHE_FLAT,
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.writeable_reg = mlxplat_mlxcpld_writeable_reg,
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.readable_reg = mlxplat_mlxcpld_readable_reg,
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.volatile_reg = mlxplat_mlxcpld_volatile_reg,
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.reg_defaults = mlxplat_mlxcpld_regmap_ng400,
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.num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400),
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.reg_read = mlxplat_mlxcpld_reg_read,
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.reg_write = mlxplat_mlxcpld_reg_write,
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};
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static struct resource mlxplat_mlxcpld_resources[] = {
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[0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"),
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};
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@ -2258,6 +2406,32 @@ static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi)
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return 1;
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}
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static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi)
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{
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int i;
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mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
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mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
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mlxplat_mux_data = mlxplat_default_mux_data;
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for (i = 0; i < mlxplat_mux_num; i++) {
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mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
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mlxplat_mux_data[i].n_values =
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ARRAY_SIZE(mlxplat_msn21xx_channels);
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}
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mlxplat_hotplug = &mlxplat_mlxcpld_ext_data;
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mlxplat_hotplug->deferred_nr =
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mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
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mlxplat_led = &mlxplat_default_ng_led_data;
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mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
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mlxplat_fan = &mlxplat_default_fan_data;
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for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
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mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
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mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
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mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
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return 1;
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}
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static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
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{
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.callback = mlxplat_dmi_default_matched,
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@ -2301,6 +2475,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
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DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"),
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},
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},
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{
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.callback = mlxplat_dmi_ng400_matched,
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.matches = {
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DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
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},
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},
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{
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.callback = mlxplat_dmi_msn274x_matched,
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.matches = {
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