soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
The Tegra20 fuse driver is the only user of tegra_apb_readl_using_dma(). Therefore we can simply the code by incorporating the APB DMA handling into the driver directly. tegra_apb_writel_using_dma() is dropped because there are no users. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>hifive-unleashed-5.1
Peter De Schrijver
Thierry Reding
parent
155dfc7b54
commit
0d827a4343
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@ -5,7 +5,6 @@ obj-y += irq.o
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obj-y += pmc.o
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obj-y += flowctrl.o
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obj-y += powergate.o
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obj-y += apbio.o
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obj-y += pm.o
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obj-y += reset.o
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obj-y += reset-handler.o
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@ -1,217 +0,0 @@
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/*
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* Copyright (C) 2010 NVIDIA Corporation.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/completion.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include "apbio.h"
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#include "iomap.h"
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#if defined(CONFIG_TEGRA20_APB_DMA)
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static DEFINE_MUTEX(tegra_apb_dma_lock);
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static u32 *tegra_apb_bb;
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static dma_addr_t tegra_apb_bb_phys;
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static DECLARE_COMPLETION(tegra_apb_wait);
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static int tegra_apb_readl_direct(unsigned long offset, u32 *value);
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static int tegra_apb_writel_direct(u32 value, unsigned long offset);
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static struct dma_chan *tegra_apb_dma_chan;
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static struct dma_slave_config dma_sconfig;
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static bool tegra_apb_dma_init(void)
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{
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dma_cap_mask_t mask;
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mutex_lock(&tegra_apb_dma_lock);
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/* Check to see if we raced to setup */
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if (tegra_apb_dma_chan)
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goto skip_init;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL);
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if (!tegra_apb_dma_chan) {
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/*
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* This is common until the device is probed, so don't
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* shout about it.
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*/
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pr_debug("%s: can not allocate dma channel\n", __func__);
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goto err_dma_alloc;
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}
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tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
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&tegra_apb_bb_phys, GFP_KERNEL);
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if (!tegra_apb_bb) {
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pr_err("%s: can not allocate bounce buffer\n", __func__);
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goto err_buff_alloc;
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}
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dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dma_sconfig.src_maxburst = 1;
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dma_sconfig.dst_maxburst = 1;
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skip_init:
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mutex_unlock(&tegra_apb_dma_lock);
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return true;
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err_buff_alloc:
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dma_release_channel(tegra_apb_dma_chan);
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tegra_apb_dma_chan = NULL;
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err_dma_alloc:
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mutex_unlock(&tegra_apb_dma_lock);
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return false;
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}
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static void apb_dma_complete(void *args)
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{
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complete(&tegra_apb_wait);
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}
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static int do_dma_transfer(unsigned long apb_add,
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enum dma_transfer_direction dir)
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{
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struct dma_async_tx_descriptor *dma_desc;
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int ret;
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if (dir == DMA_DEV_TO_MEM)
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dma_sconfig.src_addr = apb_add;
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else
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dma_sconfig.dst_addr = apb_add;
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ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig);
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if (ret)
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return ret;
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dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan,
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tegra_apb_bb_phys, sizeof(u32), dir,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma_desc)
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return -EINVAL;
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dma_desc->callback = apb_dma_complete;
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dma_desc->callback_param = NULL;
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reinit_completion(&tegra_apb_wait);
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dmaengine_submit(dma_desc);
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dma_async_issue_pending(tegra_apb_dma_chan);
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ret = wait_for_completion_timeout(&tegra_apb_wait,
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msecs_to_jiffies(50));
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if (WARN(ret == 0, "apb read dma timed out")) {
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dmaengine_terminate_all(tegra_apb_dma_chan);
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return -EFAULT;
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}
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return 0;
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}
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int tegra_apb_readl_using_dma(unsigned long offset, u32 *value)
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{
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int ret;
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if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
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return tegra_apb_readl_direct(offset, value);
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mutex_lock(&tegra_apb_dma_lock);
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ret = do_dma_transfer(offset, DMA_DEV_TO_MEM);
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if (ret < 0)
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pr_err("error in reading offset 0x%08lx using dma\n", offset);
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else
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*value = *tegra_apb_bb;
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mutex_unlock(&tegra_apb_dma_lock);
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return ret;
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}
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int tegra_apb_writel_using_dma(u32 value, unsigned long offset)
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{
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int ret;
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if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
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return tegra_apb_writel_direct(value, offset);
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mutex_lock(&tegra_apb_dma_lock);
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*((u32 *)tegra_apb_bb) = value;
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ret = do_dma_transfer(offset, DMA_MEM_TO_DEV);
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mutex_unlock(&tegra_apb_dma_lock);
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if (ret < 0)
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pr_err("error in writing offset 0x%08lx using dma\n", offset);
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return ret;
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}
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#else
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#define tegra_apb_readl_using_dma tegra_apb_readl_direct
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#define tegra_apb_writel_using_dma tegra_apb_writel_direct
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#endif
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typedef int (*apbio_read_fptr)(unsigned long offset, u32 *value);
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typedef int (*apbio_write_fptr)(u32 value, unsigned long offset);
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static apbio_read_fptr apbio_read;
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static apbio_write_fptr apbio_write;
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static int tegra_apb_readl_direct(unsigned long offset, u32 *value)
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{
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*value = readl(IO_ADDRESS(offset));
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return 0;
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}
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static int tegra_apb_writel_direct(u32 value, unsigned long offset)
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{
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writel(value, IO_ADDRESS(offset));
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return 0;
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}
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void tegra_apb_io_init(void)
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{
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/* Need to use dma only when it is Tegra20 based platform */
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if (of_machine_is_compatible("nvidia,tegra20") ||
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!of_have_populated_dt()) {
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apbio_read = tegra_apb_readl_using_dma;
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apbio_write = tegra_apb_writel_using_dma;
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} else {
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apbio_read = tegra_apb_readl_direct;
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apbio_write = tegra_apb_writel_direct;
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}
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}
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u32 tegra_apb_readl(unsigned long offset)
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{
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u32 val;
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if (apbio_read(offset, &val) < 0)
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return 0;
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else
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return val;
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}
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void tegra_apb_writel(u32 value, unsigned long offset)
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{
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apbio_write(value, offset);
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}
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@ -1,22 +0,0 @@
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/*
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* Copyright (C) 2010 NVIDIA Corporation.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_APBIO_H
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#define __MACH_TEGRA_APBIO_H
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void tegra_apb_io_init(void);
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u32 tegra_apb_readl(unsigned long offset);
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void tegra_apb_writel(u32 value, unsigned long offset);
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#endif
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@ -44,7 +44,6 @@
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#include <asm/setup.h>
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#include <asm/trusted_foundations.h>
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#include "apbio.h"
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#include "board.h"
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#include "common.h"
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#include "cpuidle.h"
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@ -74,7 +73,6 @@ u32 tegra_uart_config[3] = {
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static void __init tegra_init_early(void)
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{
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of_register_trusted_foundations();
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tegra_apb_io_init();
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tegra_init_fuse();
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tegra_cpu_reset_handler_init();
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tegra_powergate_init();
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@ -18,6 +18,9 @@
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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@ -39,18 +42,58 @@ static phys_addr_t fuse_phys;
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static struct clk *fuse_clk;
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static void __iomem __initdata *fuse_base;
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static DEFINE_MUTEX(apb_dma_lock);
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static DECLARE_COMPLETION(apb_dma_wait);
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static struct dma_chan *apb_dma_chan;
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static struct dma_slave_config dma_sconfig;
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static u32 *apb_buffer;
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static dma_addr_t apb_buffer_phys;
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static void apb_dma_complete(void *args)
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{
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complete(&apb_dma_wait);
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}
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static u32 tegra20_fuse_readl(const unsigned int offset)
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{
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int ret;
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u32 val;
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u32 val = 0;
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struct dma_async_tx_descriptor *dma_desc;
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mutex_lock(&apb_dma_lock);
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dma_sconfig.src_addr = fuse_phys + FUSE_BEGIN + offset;
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ret = dmaengine_slave_config(apb_dma_chan, &dma_sconfig);
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if (ret)
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goto out;
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dma_desc = dmaengine_prep_slave_single(apb_dma_chan, apb_buffer_phys,
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sizeof(u32), DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma_desc)
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goto out;
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dma_desc->callback = apb_dma_complete;
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dma_desc->callback_param = NULL;
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reinit_completion(&apb_dma_wait);
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clk_prepare_enable(fuse_clk);
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ret = tegra_apb_readl_using_dma(fuse_phys + FUSE_BEGIN + offset, &val);
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dmaengine_submit(dma_desc);
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dma_async_issue_pending(apb_dma_chan);
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ret = wait_for_completion_timeout(&apb_dma_wait, msecs_to_jiffies(50));
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if (WARN(ret == 0, "apb read dma timed out"))
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dmaengine_terminate_all(apb_dma_chan);
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else
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val = *apb_buffer;
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clk_disable_unprepare(fuse_clk);
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out:
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mutex_unlock(&apb_dma_lock);
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return (ret < 0) ? 0 : val;
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return val;
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}
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static const struct of_device_id tegra20_fuse_of_match[] = {
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@ -58,9 +101,35 @@ static const struct of_device_id tegra20_fuse_of_match[] = {
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{},
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};
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static int apb_dma_init(void)
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{
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dma_cap_mask_t mask;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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apb_dma_chan = dma_request_channel(mask, NULL, NULL);
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if (!apb_dma_chan)
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return -EPROBE_DEFER;
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apb_buffer = dma_alloc_coherent(NULL, sizeof(u32), &apb_buffer_phys,
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GFP_KERNEL);
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if (!apb_buffer) {
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dma_release_channel(apb_dma_chan);
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return -ENOMEM;
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}
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dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dma_sconfig.src_maxburst = 1;
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dma_sconfig.dst_maxburst = 1;
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return 0;
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}
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static int tegra20_fuse_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int err;
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fuse_clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(fuse_clk)) {
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@ -73,6 +142,10 @@ static int tegra20_fuse_probe(struct platform_device *pdev)
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return -EINVAL;
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fuse_phys = res->start;
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err = apb_dma_init();
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if (err)
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return err;
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if (tegra_fuse_create_sysfs(&pdev->dev, FUSE_SIZE, tegra20_fuse_readl))
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return -ENODEV;
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@ -61,20 +61,6 @@ int tegra_fuse_readl(unsigned long offset, u32 *value);
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extern struct tegra_sku_info tegra_sku_info;
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#if defined(CONFIG_TEGRA20_APB_DMA)
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int tegra_apb_readl_using_dma(unsigned long offset, u32 *value);
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int tegra_apb_writel_using_dma(u32 value, unsigned long offset);
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#else
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static inline int tegra_apb_readl_using_dma(unsigned long offset, u32 *value)
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{
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return -EINVAL;
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}
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static inline int tegra_apb_writel_using_dma(u32 value, unsigned long offset)
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{
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return -EINVAL;
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}
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#endif /* CONFIG_TEGRA20_APB_DMA */
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#endif /* __ASSEMBLY__ */
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#endif /* __SOC_TEGRA_FUSE_H__ */
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