drm/i915/hsw: Set correct Haswell PTE encodings.
The cacheability controls have changed, and the bits have been rearranged in general. Note that age 0 is the oldest (most likely to get evicted) and age 3 is the youngest (most likely to stick around for a bit). We've picked 0 for no reason, but atm it shouldn't matter anyway (since we don't yet try to differentiate between different objects). v2: Remove comments for snb/ivb cache leves, that's a separate change. v3: Resolve conflicts due to patch series reordering. v4: Rebased on top of Kenneth Graunke's ->pte_encode refactoring. v5: Removed eLLC bits for separate patch. In the internal repository this was: Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Add comment about cache ages as requested by Ben provoked due to a question from Damien.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -33,6 +33,7 @@
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/* PPGTT stuff */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
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#define GEN6_PDE_VALID (1 << 0)
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/* gen6+ has bit 11-4 for physical addr bit 39-32 */
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@ -44,6 +45,14 @@
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
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/* Cacheability Control is a 4-bit value. The low three bits are stored in *
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* bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
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*/
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#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
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(((bits) & 0x8) << (11 - 3)))
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#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
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static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,
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enum i915_cache_level level)
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@ -92,10 +101,10 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
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enum i915_cache_level level)
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{
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gen6_gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= GEN6_PTE_ADDR_ENCODE(addr);
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pte |= HSW_PTE_ADDR_ENCODE(addr);
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if (level != I915_CACHE_NONE)
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pte |= GEN6_PTE_CACHE_LLC;
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pte |= HSW_WB_LLC_AGE0;
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return pte;
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}
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