[PATCH] Add Myri-10G Ethernet driver
Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Andrew J. Gallatin <gallatin@myri.com> drivers/net/Kconfig | 17 drivers/net/Makefile | 1 drivers/net/myri10ge/Makefile | 5 drivers/net/myri10ge/myri10ge.c | 2851 +++++++++++++++ drivers/net/myri10ge/myri10ge_mcp.h | 205 + drivers/net/myri10ge/myri10ge_mcp_gen_header.h | 58 include/linux/pci_ids.h | 1 7 files changed, 3138 insertions(+) Signed-off-by: Jeff Garzik <jeff@garzik.org>hifive-unleashed-5.1
Brice Goglin
Jeff Garzik
parent
3a720d726a
commit
0da34b6dfe
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@ -2327,6 +2327,23 @@ config S2IO_NAPI
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If in doubt, say N.
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config MYRI10GE
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tristate "Myricom Myri-10G Ethernet support"
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depends on PCI
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select FW_LOADER
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select CRC32
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---help---
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This driver supports Myricom Myri-10G Dual Protocol interface in
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Ethernet mode. If the eeprom on your board is not recent enough,
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you will need a newer firmware image.
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You may get this image or more information, at:
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<http://www.myri.com/Myri-10G/>
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To compile this driver as a module, choose M here and read
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<file:Documentation/networking/net-modules.txt>. The module
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will be called myri10ge.
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endmenu
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source "drivers/net/tokenring/Kconfig"
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@ -192,6 +192,7 @@ obj-$(CONFIG_R8169) += r8169.o
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obj-$(CONFIG_AMD8111_ETH) += amd8111e.o
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obj-$(CONFIG_IBMVETH) += ibmveth.o
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obj-$(CONFIG_S2IO) += s2io.o
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obj-$(CONFIG_MYRI10GE) += myri10ge/
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obj-$(CONFIG_SMC91X) += smc91x.o
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obj-$(CONFIG_SMC911X) += smc911x.o
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obj-$(CONFIG_DM9000) += dm9000.o
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@ -0,0 +1,5 @@
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#
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# Makefile for the Myricom Myri-10G ethernet driver
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#
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obj-$(CONFIG_MYRI10GE) += myri10ge.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,205 @@
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#ifndef __MYRI10GE_MCP_H__
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#define __MYRI10GE_MCP_H__
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#define MXGEFW_VERSION_MAJOR 1
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#define MXGEFW_VERSION_MINOR 4
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/* 8 Bytes */
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struct mcp_dma_addr {
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u32 high;
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u32 low;
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};
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/* 4 Bytes */
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struct mcp_slot {
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u16 checksum;
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u16 length;
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};
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/* 64 Bytes */
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struct mcp_cmd {
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u32 cmd;
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u32 data0; /* will be low portion if data > 32 bits */
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/* 8 */
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u32 data1; /* will be high portion if data > 32 bits */
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u32 data2; /* currently unused.. */
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/* 16 */
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struct mcp_dma_addr response_addr;
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/* 24 */
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u8 pad[40];
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};
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/* 8 Bytes */
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struct mcp_cmd_response {
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u32 data;
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u32 result;
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};
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/*
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* flags used in mcp_kreq_ether_send_t:
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*
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* The SMALL flag is only needed in the first segment. It is raised
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* for packets that are total less or equal 512 bytes.
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*
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* The CKSUM flag must be set in all segments.
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*
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* The PADDED flags is set if the packet needs to be padded, and it
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* must be set for all segments.
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*
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* The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
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* length of all previous segments was odd.
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*/
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#define MXGEFW_FLAGS_SMALL 0x1
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#define MXGEFW_FLAGS_TSO_HDR 0x1
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#define MXGEFW_FLAGS_FIRST 0x2
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#define MXGEFW_FLAGS_ALIGN_ODD 0x4
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#define MXGEFW_FLAGS_CKSUM 0x8
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#define MXGEFW_FLAGS_TSO_LAST 0x8
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#define MXGEFW_FLAGS_NO_TSO 0x10
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#define MXGEFW_FLAGS_TSO_CHOP 0x10
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#define MXGEFW_FLAGS_TSO_PLD 0x20
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#define MXGEFW_SEND_SMALL_SIZE 1520
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#define MXGEFW_MAX_MTU 9400
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union mcp_pso_or_cumlen {
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u16 pseudo_hdr_offset;
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u16 cum_len;
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};
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#define MXGEFW_MAX_SEND_DESC 12
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#define MXGEFW_PAD 2
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/* 16 Bytes */
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struct mcp_kreq_ether_send {
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u32 addr_high;
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u32 addr_low;
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u16 pseudo_hdr_offset;
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u16 length;
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u8 pad;
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u8 rdma_count;
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u8 cksum_offset; /* where to start computing cksum */
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u8 flags; /* as defined above */
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};
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/* 8 Bytes */
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struct mcp_kreq_ether_recv {
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u32 addr_high;
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u32 addr_low;
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};
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/* Commands */
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#define MXGEFW_CMD_OFFSET 0xf80000
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enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_NONE = 0,
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/* Reset the mcp, it is left in a safe state, waiting
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* for the driver to set all its parameters */
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MXGEFW_CMD_RESET,
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/* get the version number of the current firmware..
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* (may be available in the eeprom strings..? */
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MXGEFW_GET_MCP_VERSION,
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/* Parameters which must be set by the driver before it can
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* issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
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* MXGEFW_CMD_RESET is issued */
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MXGEFW_CMD_SET_INTRQ_DMA,
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MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */
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MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */
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/* Parameters which refer to lanai SRAM addresses where the
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* driver must issue PIO writes for various things */
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MXGEFW_CMD_GET_SEND_OFFSET,
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MXGEFW_CMD_GET_SMALL_RX_OFFSET,
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MXGEFW_CMD_GET_BIG_RX_OFFSET,
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MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
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MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
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/* Parameters which refer to rings stored on the MCP,
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* and whose size is controlled by the mcp */
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MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */
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MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */
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/* Parameters which refer to rings stored in the host,
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* and whose size is controlled by the host. Note that
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* all must be physically contiguous and must contain
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* a power of 2 number of entries. */
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MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */
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/* command to bring ethernet interface up. Above parameters
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* (plus mtu & mac address) must have been exchanged prior
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* to issuing this command */
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MXGEFW_CMD_ETHERNET_UP,
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/* command to bring ethernet interface down. No further sends
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* or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
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* is issued, and all interrupt queues must be flushed prior
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* to ack'ing this command */
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MXGEFW_CMD_ETHERNET_DOWN,
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/* commands the driver may issue live, without resetting
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* the nic. Note that increasing the mtu "live" should
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* only be done if the driver has already supplied buffers
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* sufficiently large to handle the new mtu. Decreasing
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* the mtu live is safe */
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MXGEFW_CMD_SET_MTU,
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MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */
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MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */
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MXGEFW_CMD_SET_STATS_DMA,
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MXGEFW_ENABLE_PROMISC,
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MXGEFW_DISABLE_PROMISC,
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MXGEFW_SET_MAC_ADDRESS,
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MXGEFW_ENABLE_FLOW_CONTROL,
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MXGEFW_DISABLE_FLOW_CONTROL,
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/* do a DMA test
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* data0,data1 = DMA address
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* data2 = RDMA length (MSH), WDMA length (LSH)
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* command return data = repetitions (MSH), 0.5-ms ticks (LSH)
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*/
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MXGEFW_DMA_TEST
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};
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enum myri10ge_mcp_cmd_status {
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MXGEFW_CMD_OK = 0,
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MXGEFW_CMD_UNKNOWN,
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MXGEFW_CMD_ERROR_RANGE,
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MXGEFW_CMD_ERROR_BUSY,
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MXGEFW_CMD_ERROR_EMPTY,
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MXGEFW_CMD_ERROR_CLOSED,
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MXGEFW_CMD_ERROR_HASH_ERROR,
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MXGEFW_CMD_ERROR_BAD_PORT,
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MXGEFW_CMD_ERROR_RESOURCES
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};
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/* 40 Bytes */
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struct mcp_irq_data {
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u32 send_done_count;
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u32 link_up;
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u32 dropped_link_overflow;
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u32 dropped_link_error_or_filtered;
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u32 dropped_runt;
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u32 dropped_overrun;
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u32 dropped_no_small_buffer;
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u32 dropped_no_big_buffer;
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u32 rdma_tags_available;
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u8 tx_stopped;
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u8 link_down;
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u8 stats_updated;
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u8 valid;
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};
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#endif /* __MYRI10GE_MCP_H__ */
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@ -0,0 +1,58 @@
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#ifndef __MYRI10GE_MCP_GEN_HEADER_H__
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#define __MYRI10GE_MCP_GEN_HEADER_H__
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/* this file define a standard header used as a first entry point to
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* exchange information between firmware/driver and driver. The
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* header structure can be anywhere in the mcp. It will usually be in
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* the .data section, because some fields needs to be initialized at
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* compile time.
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* The 32bit word at offset MX_HEADER_PTR_OFFSET in the mcp must
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* contains the location of the header.
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*
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* Typically a MCP will start with the following:
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* .text
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* .space 52 ! to help catch MEMORY_INT errors
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* bt start ! jump to real code
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* nop
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* .long _gen_mcp_header
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*
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* The source will have a definition like:
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*
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* mcp_gen_header_t gen_mcp_header = {
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* .header_length = sizeof(mcp_gen_header_t),
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* .mcp_type = MCP_TYPE_XXX,
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* .version = "something $Id: mcp_gen_header.h,v 1.2 2006/05/13 10:04:35 bgoglin Exp $",
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* .mcp_globals = (unsigned)&Globals
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* };
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*/
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#define MCP_HEADER_PTR_OFFSET 0x3c
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#define MCP_TYPE_MX 0x4d582020 /* "MX " */
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#define MCP_TYPE_PCIE 0x70636965 /* "PCIE" pcie-only MCP */
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#define MCP_TYPE_ETH 0x45544820 /* "ETH " */
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#define MCP_TYPE_MCP0 0x4d435030 /* "MCP0" */
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struct mcp_gen_header {
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/* the first 4 fields are filled at compile time */
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unsigned header_length;
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unsigned mcp_type;
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char version[128];
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unsigned mcp_globals; /* pointer to mcp-type specific structure */
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/* filled by the MCP at run-time */
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unsigned sram_size;
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unsigned string_specs; /* either the original STRING_SPECS or a superset */
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unsigned string_specs_len;
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/* Fields above this comment are guaranteed to be present.
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*
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* Fields below this comment are extensions added in later versions
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* of this struct, drivers should compare the header_length against
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* offsetof(field) to check wether a given MCP implements them.
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*
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* Never remove any field. Keep everything naturally align.
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*/
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};
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#endif /* __MYRI10GE_MCP_GEN_HEADER_H__ */
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@ -1827,6 +1827,7 @@
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#define PCI_VENDOR_ID_SAMSUNG 0x144d
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#define PCI_VENDOR_ID_MYRICOM 0x14c1
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#define PCI_VENDOR_ID_TITAN 0x14D2
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#define PCI_DEVICE_ID_TITAN_010L 0x8001
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